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| author | Mike Pall <mike> | 2010-01-27 03:50:29 +0100 |
|---|---|---|
| committer | Mike Pall <mike> | 2010-01-27 03:50:29 +0100 |
| commit | 3aeb89226202439c0be07830ae6e71007a7b5dd3 (patch) | |
| tree | 77789041551fc1b5bcb2eb69c85e9b221a49d578 /src/lj_asm.c | |
| parent | d216cdb2b9eb41879cdfc327486d805cc260d8fa (diff) | |
| download | luajit-3aeb89226202439c0be07830ae6e71007a7b5dd3.tar.gz luajit-3aeb89226202439c0be07830ae6e71007a7b5dd3.tar.bz2 luajit-3aeb89226202439c0be07830ae6e71007a7b5dd3.zip | |
Eliminate IR_FRAME. Replace with KGC and TRef/SnapEntry flags.
Diffstat (limited to 'src/lj_asm.c')
| -rw-r--r-- | src/lj_asm.c | 67 |
1 files changed, 28 insertions, 39 deletions
diff --git a/src/lj_asm.c b/src/lj_asm.c index 3912bbeb..48b6ec5a 100644 --- a/src/lj_asm.c +++ b/src/lj_asm.c | |||
| @@ -931,7 +931,7 @@ static void asm_snap_alloc(ASMState *as) | |||
| 931 | IRRef ref = snap_ref(map[n]); | 931 | IRRef ref = snap_ref(map[n]); |
| 932 | if (!irref_isk(ref)) { | 932 | if (!irref_isk(ref)) { |
| 933 | IRIns *ir = IR(ref); | 933 | IRIns *ir = IR(ref); |
| 934 | if (!ra_used(ir) && ir->o != IR_FRAME) { | 934 | if (!ra_used(ir)) { |
| 935 | RegSet allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR; | 935 | RegSet allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR; |
| 936 | /* Not a var-to-invar ref and got a free register (or a remat)? */ | 936 | /* Not a var-to-invar ref and got a free register (or a remat)? */ |
| 937 | if ((!iscrossref(as, ref) || irt_isphi(ir->t)) && | 937 | if ((!iscrossref(as, ref) || irt_isphi(ir->t)) && |
| @@ -2831,27 +2831,25 @@ static void asm_head_side(ASMState *as) | |||
| 2831 | /* Scan all parent SLOADs and collect register dependencies. */ | 2831 | /* Scan all parent SLOADs and collect register dependencies. */ |
| 2832 | for (i = as->curins; i > REF_BASE; i--) { | 2832 | for (i = as->curins; i > REF_BASE; i--) { |
| 2833 | IRIns *ir = IR(i); | 2833 | IRIns *ir = IR(i); |
| 2834 | lua_assert((ir->o == IR_SLOAD && (ir->op2 & IRSLOAD_PARENT)) || | 2834 | RegSP rs; |
| 2835 | ir->o == IR_FRAME); | 2835 | lua_assert(ir->o == IR_SLOAD && (ir->op2 & IRSLOAD_PARENT)); |
| 2836 | if (ir->o == IR_SLOAD) { | 2836 | rs = as->parentmap[ir->op1]; |
| 2837 | RegSP rs = as->parentmap[ir->op1]; | 2837 | if (ra_hasreg(ir->r)) { |
| 2838 | if (ra_hasreg(ir->r)) { | 2838 | rset_clear(allow, ir->r); |
| 2839 | rset_clear(allow, ir->r); | 2839 | if (ra_hasspill(ir->s)) |
| 2840 | if (ra_hasspill(ir->s)) | 2840 | ra_save(as, ir, ir->r); |
| 2841 | ra_save(as, ir, ir->r); | 2841 | } else if (ra_hasspill(ir->s)) { |
| 2842 | } else if (ra_hasspill(ir->s)) { | 2842 | irt_setmark(ir->t); |
| 2843 | irt_setmark(ir->t); | 2843 | pass2 = 1; |
| 2844 | pass2 = 1; | 2844 | } |
| 2845 | } | 2845 | if (ir->r == rs) { /* Coalesce matching registers right now. */ |
| 2846 | if (ir->r == rs) { /* Coalesce matching registers right now. */ | 2846 | ra_free(as, ir->r); |
| 2847 | ra_free(as, ir->r); | 2847 | } else if (ra_hasspill(regsp_spill(rs))) { |
| 2848 | } else if (ra_hasspill(regsp_spill(rs))) { | 2848 | if (ra_hasreg(ir->r)) |
| 2849 | if (ra_hasreg(ir->r)) | 2849 | pass3 = 1; |
| 2850 | pass3 = 1; | 2850 | } else if (ra_used(ir)) { |
| 2851 | } else if (ra_used(ir)) { | 2851 | sloadins[rs] = (IRRef1)i; |
| 2852 | sloadins[rs] = (IRRef1)i; | 2852 | rset_set(live, rs); /* Block live parent register. */ |
| 2853 | rset_set(live, rs); /* Block live parent register. */ | ||
| 2854 | } | ||
| 2855 | } | 2853 | } |
| 2856 | } | 2854 | } |
| 2857 | 2855 | ||
| @@ -2979,8 +2977,7 @@ static void asm_tail_sync(ASMState *as) | |||
| 2979 | SnapEntry sn = map[n]; | 2977 | SnapEntry sn = map[n]; |
| 2980 | if ((sn & SNAP_FRAME)) { | 2978 | if ((sn & SNAP_FRAME)) { |
| 2981 | IRIns *ir = IR(snap_ref(sn)); | 2979 | IRIns *ir = IR(snap_ref(sn)); |
| 2982 | GCfunc *fn = ir_kfunc(IR(ir->op2)); | 2980 | GCfunc *fn = ir_kfunc(ir); |
| 2983 | lua_assert(ir->o == IR_FRAME && irt_isfunc(ir->t)); | ||
| 2984 | if (isluafunc(fn)) { | 2981 | if (isluafunc(fn)) { |
| 2985 | BCReg s = snap_slot(sn); | 2982 | BCReg s = snap_slot(sn); |
| 2986 | BCReg fs = s + funcproto(fn)->framesize; | 2983 | BCReg fs = s + funcproto(fn)->framesize; |
| @@ -3019,9 +3016,10 @@ static void asm_tail_sync(ASMState *as) | |||
| 3019 | 3016 | ||
| 3020 | /* Store the value of all modified slots to the Lua stack. */ | 3017 | /* Store the value of all modified slots to the Lua stack. */ |
| 3021 | for (n = 0; n < nent; n++) { | 3018 | for (n = 0; n < nent; n++) { |
| 3022 | BCReg s = snap_slot(map[n]); | 3019 | SnapEntry sn = map[n]; |
| 3020 | BCReg s = snap_slot(sn); | ||
| 3023 | int32_t ofs = 8*((int32_t)s-1); | 3021 | int32_t ofs = 8*((int32_t)s-1); |
| 3024 | IRRef ref = snap_ref(map[n]); | 3022 | IRRef ref = snap_ref(sn); |
| 3025 | IRIns *ir = IR(ref); | 3023 | IRIns *ir = IR(ref); |
| 3026 | /* No need to restore readonly slots and unmodified non-parent slots. */ | 3024 | /* No need to restore readonly slots and unmodified non-parent slots. */ |
| 3027 | if (ir->o == IR_SLOAD && ir->op1 == s && | 3025 | if (ir->o == IR_SLOAD && ir->op1 == s && |
| @@ -3030,10 +3028,6 @@ static void asm_tail_sync(ASMState *as) | |||
| 3030 | if (irt_isnum(ir->t)) { | 3028 | if (irt_isnum(ir->t)) { |
| 3031 | Reg src = ra_alloc1(as, ref, RSET_FPR); | 3029 | Reg src = ra_alloc1(as, ref, RSET_FPR); |
| 3032 | emit_rmro(as, XO_MOVSDto, src, RID_BASE, ofs); | 3030 | emit_rmro(as, XO_MOVSDto, src, RID_BASE, ofs); |
| 3033 | } else if (ir->o == IR_FRAME) { | ||
| 3034 | emit_movmroi(as, RID_BASE, ofs, ptr2addr(ir_kgc(IR(ir->op2)))); | ||
| 3035 | if (s != 0) /* Do not overwrite link to previous frame. */ | ||
| 3036 | emit_movmroi(as, RID_BASE, ofs+4, (int32_t)(*--flinks)); | ||
| 3037 | } else { | 3031 | } else { |
| 3038 | lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t)); | 3032 | lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t)); |
| 3039 | if (!irref_isk(ref)) { | 3033 | if (!irref_isk(ref)) { |
| @@ -3042,7 +3036,10 @@ static void asm_tail_sync(ASMState *as) | |||
| 3042 | } else if (!irt_ispri(ir->t)) { | 3036 | } else if (!irt_ispri(ir->t)) { |
| 3043 | emit_movmroi(as, RID_BASE, ofs, ir->i); | 3037 | emit_movmroi(as, RID_BASE, ofs, ir->i); |
| 3044 | } | 3038 | } |
| 3045 | emit_movmroi(as, RID_BASE, ofs+4, irt_toitype(ir->t)); | 3039 | if (!(sn & (SNAP_CONT|SNAP_FRAME))) |
| 3040 | emit_movmroi(as, RID_BASE, ofs+4, irt_toitype(ir->t)); | ||
| 3041 | else if (s != 0) /* Do not overwrite link to previous frame. */ | ||
| 3042 | emit_movmroi(as, RID_BASE, ofs+4, (int32_t)(*--flinks)); | ||
| 3046 | } | 3043 | } |
| 3047 | checkmclim(as); | 3044 | checkmclim(as); |
| 3048 | } | 3045 | } |
| @@ -3110,10 +3107,6 @@ static void asm_ir(ASMState *as, IRIns *ir) | |||
| 3110 | case IR_ULE: asm_comp(as, ir, CC_A, CC_A, VCC_U); break; | 3107 | case IR_ULE: asm_comp(as, ir, CC_A, CC_A, VCC_U); break; |
| 3111 | case IR_ABC: | 3108 | case IR_ABC: |
| 3112 | case IR_UGT: asm_comp(as, ir, CC_BE, CC_BE, VCC_U|VCC_PS); break; | 3109 | case IR_UGT: asm_comp(as, ir, CC_BE, CC_BE, VCC_U|VCC_PS); break; |
| 3113 | |||
| 3114 | case IR_FRAME: | ||
| 3115 | if (ir->op1 == ir->op2) break; /* No check needed for placeholder. */ | ||
| 3116 | /* fallthrough */ | ||
| 3117 | case IR_EQ: asm_comp(as, ir, CC_NE, CC_NE, VCC_P); break; | 3110 | case IR_EQ: asm_comp(as, ir, CC_NE, CC_NE, VCC_P); break; |
| 3118 | case IR_NE: asm_comp(as, ir, CC_E, CC_E, VCC_U|VCC_P); break; | 3111 | case IR_NE: asm_comp(as, ir, CC_E, CC_E, VCC_U|VCC_P); break; |
| 3119 | 3112 | ||
| @@ -3272,10 +3265,6 @@ static void asm_setup_regsp(ASMState *as, Trace *T) | |||
| 3272 | } | 3265 | } |
| 3273 | } | 3266 | } |
| 3274 | break; | 3267 | break; |
| 3275 | case IR_FRAME: | ||
| 3276 | if (i == as->stopins+1 && ir->op1 == ir->op2) | ||
| 3277 | as->stopins++; | ||
| 3278 | break; | ||
| 3279 | case IR_CALLN: case IR_CALLL: case IR_CALLS: { | 3268 | case IR_CALLN: case IR_CALLL: case IR_CALLS: { |
| 3280 | const CCallInfo *ci = &lj_ir_callinfo[ir->op2]; | 3269 | const CCallInfo *ci = &lj_ir_callinfo[ir->op2]; |
| 3281 | /* NYI: not fastcall-aware, but doesn't matter (yet). */ | 3270 | /* NYI: not fastcall-aware, but doesn't matter (yet). */ |