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authorMike Pall <mike>2012-01-23 22:20:28 +0100
committerMike Pall <mike>2012-01-23 22:24:11 +0100
commit5bed11e6b4c2bbf0cbec0f00efe998289236b217 (patch)
tree5ed76367d5157df37b358a5874d34a21dc7d60b0 /src/lj_target_mips.h
parent7d2774e4c5ee7c649ccb41f75bfbbb1e7f370a96 (diff)
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MIPS: Add interpreter. Enable MIPS build rules.
Diffstat (limited to 'src/lj_target_mips.h')
-rw-r--r--src/lj_target_mips.h153
1 files changed, 153 insertions, 0 deletions
diff --git a/src/lj_target_mips.h b/src/lj_target_mips.h
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1/*
2** Definitions for MIPS CPUs.
3** Copyright (C) 2005-2012 Mike Pall. See Copyright Notice in luajit.h
4*/
5
6#ifndef _LJ_TARGET_MIPS_H
7#define _LJ_TARGET_MIPS_H
8
9/* -- Registers IDs ------------------------------------------------------- */
10
11#define GPRDEF(_) \
12 _(R0) _(R1) _(R2) _(R3) _(R4) _(R5) _(R6) _(R7) \
13 _(R8) _(R9) _(R10) _(R11) _(R12) _(R13) _(R14) _(R15) \
14 _(R16) _(R17) _(R18) _(R19) _(R20) _(R21) _(R22) _(R23) \
15 _(R24) _(R25) _(SYS1) _(SYS2) _(GP) _(SP) _(R30) _(RA)
16#define FPRDEF(_) \
17 _(F0) _(F1) _(F2) _(F3) _(F4) _(F5) _(F6) _(F7) \
18 _(F8) _(F9) _(F10) _(F11) _(F12) _(F13) _(F14) _(F15) \
19 _(F16) _(F17) _(F18) _(F19) _(F20) _(F21) _(F22) _(F23) \
20 _(F24) _(F25) _(F26) _(F27) _(F28) _(F29) _(F30) _(F31)
21#define VRIDDEF(_)
22
23#define RIDENUM(name) RID_##name,
24
25enum {
26 GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
27 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
28 RID_MAX,
29 RID_TMP = RID_RA,
30
31 /* Calling conventions. */
32 RID_RET = RID_R2,
33#if LJ_LE
34 RID_RETHI = RID_R3,
35 RID_RETLO = RID_R2,
36#else
37 RID_RETHI = RID_R2,
38 RID_RETLO = RID_R3,
39#endif
40 RID_FPRET = RID_F0,
41
42 /* These definitions must match with the *.dasc file(s): */
43 RID_BASE = RID_R16, /* Interpreter BASE. */
44 RID_LPC = RID_R18, /* Interpreter PC. */
45 RID_DISPATCH = RID_R19, /* Interpreter DISPATCH table. */
46 RID_LREG = RID_R20, /* Interpreter L. */
47 RID_JGL = RID_R30, /* On-trace: global_State + 32768. */
48
49 /* Register ranges [min, max) and number of registers. */
50 RID_MIN_GPR = RID_R0,
51 RID_MAX_GPR = RID_RA+1,
52 RID_MIN_FPR = RID_F0,
53 RID_MAX_FPR = RID_F31+1,
54 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
55 RID_NUM_FPR = (RID_MAX_FPR - RID_MIN_FPR)/2
56};
57
58#define RID_NUM_KREF RID_NUM_GPR
59#define RID_MIN_KREF RID_R0
60
61/* -- Register sets ------------------------------------------------------- */
62
63/* Make use of all registers, except TMP, SP, SYS1, SYS2 and JGL. */
64#define RSET_FIXED \
65 (RID2RSET(RID_TMP)|RID2RSET(RID_SP)|RID2RSET(RID_SYS1)|\
66 RID2RSET(RID_SYS2)|RID2RSET(RID_JGL))
67#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED)
68#define RSET_FPR \
69 (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\
70 RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\
71 RID2RSET(RID_F16)|RID2RSET(RID_F18)|RID2RSET(RID_F20)|RID2RSET(RID_F22)|\
72 RID2RSET(RID_F24)|RID2RSET(RID_F26)|RID2RSET(RID_F28)|RID2RSET(RID_F30))
73#define RSET_ALL (RSET_GPR|RSET_FPR)
74#define RSET_INIT RSET_ALL
75
76#define RSET_SCRATCH_GPR \
77 (RSET_RANGE(RID_R1, RID_R15+1)|\
78 RID2RSET(RID_R24)|RID2RSET(RID_R25)|RID2RSET(RID_GP)|RID2RSET(RID_RA))
79#define RSET_SCRATCH_FPR \
80 (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\
81 RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\
82 RID2RSET(RID_F16)|RID2RSET(RID_F18))
83#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
84#define REGARG_FIRSTGPR RID_R4
85#define REGARG_LASTGPR RID_R7
86#define REGARG_NUMGPR 4
87#define REGARG_FIRSTFPR RID_F12
88#define REGARG_LASTFPR RID_F14
89#define REGARG_NUMFPR 2
90
91/* -- Spill slots --------------------------------------------------------- */
92
93/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
94**
95** SPS_FIXED: Available fixed spill slots in interpreter frame.
96** This definition must match with the *.dasc file(s).
97**
98** SPS_FIRST: First spill slot for general use.
99*/
100#define SPS_FIXED 5
101#define SPS_FIRST 4
102
103#define sps_scale(slot) (4 * (int32_t)(slot))
104#define sps_align(slot) (((slot) - SPS_FIXED + 1) & ~1)
105
106/* -- Exit state ---------------------------------------------------------- */
107
108/* This definition must match with the *.dasc file(s). */
109typedef struct {
110 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
111 int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
112 int32_t spill[256]; /* Spill slots. */
113} ExitState;
114
115/* Highest exit + 1 indicates stack check. */
116#define EXITSTATE_CHECKEXIT 1
117
118#define EXITSTUB_SPACING 8
119#define EXITSTUBS_PER_GROUP 16
120
121/* -- Instructions -------------------------------------------------------- */
122
123/* Instruction fields. */
124#define MIPSF_S(r) ((r) << 21)
125#define MIPSF_T(r) ((r) << 16)
126#define MIPSF_D(r) ((r) << 11)
127#define MIPSF_R(r) ((r) << 21)
128#define MIPSF_H(r) ((r) << 16)
129#define MIPSF_G(r) ((r) << 11)
130#define MIPSF_F(r) ((r) << 6)
131#define MIPSF_A(n) ((n) << 6)
132#define MIPSF_M(n) ((n) << 11)
133
134typedef enum MIPSIns {
135 /* Integer instructions. */
136 MIPSI_MOVE = 0x00000021,
137 MIPSI_NOP = 0x00000000,
138
139 MIPSI_LI = 0x24000000,
140 MIPSI_LU = 0x34000000,
141 MIPSI_LUI = 0x3c000000,
142
143 MIPSI_ORI = 0x34000000,
144
145 MIPSI_B = 0x10000000,
146 MIPSI_JR = 0x00000008,
147
148 /* Load/store instructions. */
149 MIPSI_LW = 0x8c000000,
150 MIPSI_SW = 0xac000000,
151} MIPSIns;
152
153#endif
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