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authorMike Pall <mike>2010-02-25 03:35:07 +0100
committerMike Pall <mike>2010-02-25 03:35:07 +0100
commit3c6cec0846ae25dc9d0c2495cb02316694725add (patch)
tree6900f1555f4c920f87e7d2ef23fce65051ddaf65 /src/lj_target_x86.h
parentb95294572ce8efa527e0b0118bb7168117afd171 (diff)
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Add x64 call argument setup. More 32/64 bit cleanups in assembler.
Diffstat (limited to '')
-rw-r--r--src/lj_target_x86.h26
1 files changed, 21 insertions, 5 deletions
diff --git a/src/lj_target_x86.h b/src/lj_target_x86.h
index 8e9a8788..83eba0ec 100644
--- a/src/lj_target_x86.h
+++ b/src/lj_target_x86.h
@@ -78,14 +78,27 @@ enum {
78/* Windows x64 ABI. */ 78/* Windows x64 ABI. */
79#define RSET_SCRATCH \ 79#define RSET_SCRATCH \
80 (RSET_ACD|RSET_RANGE(RID_R8D, RID_R11D+1)|RSET_RANGE(RID_XMM0, RID_XMM5+1)) 80 (RSET_ACD|RSET_RANGE(RID_R8D, RID_R11D+1)|RSET_RANGE(RID_XMM0, RID_XMM5+1))
81#define REGARG_GPRS \
82 (RID_ECX|((RID_EDX|((RID_R8D|(RID_R9D<<5))<<5))<<5))
83#define REGARG_FIRSTFPR RID_XMM0
84#define REGARG_LASTFPR RID_XMM3
85#define STACKARG_OFS (4*8)
81#else 86#else
82/* The rest of the civilized x64 world has a common ABI. */ 87/* The rest of the civilized x64 world has a common ABI. */
83#define RSET_SCRATCH \ 88#define RSET_SCRATCH \
84 (RSET_ACD|RSET_RANGE(RID_ESI, RID_R11D+1)|RSET_FPR) 89 (RSET_ACD|RSET_RANGE(RID_ESI, RID_R11D+1)|RSET_FPR)
90#define REGARG_GPRS \
91 (RID_EDI|((RID_ESI|((RID_EDX|((RID_ECX|((RID_R8D|(RID_R9D \
92 <<5))<<5))<<5))<<5))<<5))
93#define REGARG_FIRSTFPR RID_XMM0
94#define REGARG_LASTFPR RID_XMM7
95#define STACKARG_OFS 0
85#endif 96#endif
86#else 97#else
87/* Common x86 ABI. */ 98/* Common x86 ABI. */
88#define RSET_SCRATCH (RSET_ACD|RSET_FPR) 99#define RSET_SCRATCH (RSET_ACD|RSET_FPR)
100#define REGARG_GPRS (RID_ECX|(RID_EDX<<5)) /* Fastcall only. */
101#define STACKARG_OFS 0
89#endif 102#endif
90 103
91#if LJ_64 104#if LJ_64
@@ -96,23 +109,26 @@ enum {
96 109
97/* -- Spill slots --------------------------------------------------------- */ 110/* -- Spill slots --------------------------------------------------------- */
98 111
99/* Available fixed spill slots in interpreter frame. 112/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
113**
114** SPS_FIXED: Available fixed spill slots in interpreter frame.
100** This definition must match with the *.dasc file(s). 115** This definition must match with the *.dasc file(s).
116**
117** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots.
101*/ 118*/
102#if LJ_64 119#if LJ_64
103#ifdef _WIN64 120#ifdef _WIN64
104#define SPS_FIXED (5*2) 121#define SPS_FIXED (5*2)
122#define SPS_FIRST (4*2) /* Don't use callee register save area. */
105#else 123#else
106#define SPS_FIXED 2 124#define SPS_FIXED 2
125#define SPS_FIRST 2
107#endif 126#endif
108#else 127#else
109#define SPS_FIXED 6 128#define SPS_FIXED 6
110#endif
111
112/* First spill slot for general use. Reserve one 64 bit slot. */
113#define SPS_FIRST 2 129#define SPS_FIRST 2
130#endif
114 131
115/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs. */
116#define sps_scale(slot) (4 * (int32_t)(slot)) 132#define sps_scale(slot) (4 * (int32_t)(slot))
117 133
118/* -- Exit state ---------------------------------------------------------- */ 134/* -- Exit state ---------------------------------------------------------- */