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-rw-r--r--src/lj_asm_x86.h2668
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diff --git a/src/lj_asm_x86.h b/src/lj_asm_x86.h
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1/*
2** x86/x64 IR assembler (SSA IR -> machine code).
3** Copyright (C) 2005-2011 Mike Pall. See Copyright Notice in luajit.h
4*/
5
6/* -- Guard handling ------------------------------------------------------ */
7
8/* Generate an exit stub group at the bottom of the reserved MCode memory. */
9static MCode *asm_exitstub_gen(ASMState *as, ExitNo group)
10{
11 ExitNo i, groupofs = (group*EXITSTUBS_PER_GROUP) & 0xff;
12 MCode *mxp = as->mcbot;
13 MCode *mxpstart = mxp;
14 if (mxp + (2+2)*EXITSTUBS_PER_GROUP+8+5 >= as->mctop)
15 asm_mclimit(as);
16 /* Push low byte of exitno for each exit stub. */
17 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)groupofs;
18 for (i = 1; i < EXITSTUBS_PER_GROUP; i++) {
19 *mxp++ = XI_JMPs; *mxp++ = (MCode)((2+2)*(EXITSTUBS_PER_GROUP - i) - 2);
20 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)(groupofs + i);
21 }
22 /* Push the high byte of the exitno for each exit stub group. */
23 *mxp++ = XI_PUSHi8; *mxp++ = (MCode)((group*EXITSTUBS_PER_GROUP)>>8);
24 /* Store DISPATCH at original stack slot 0. Account for the two push ops. */
25 *mxp++ = XI_MOVmi;
26 *mxp++ = MODRM(XM_OFS8, 0, RID_ESP);
27 *mxp++ = MODRM(XM_SCALE1, RID_ESP, RID_ESP);
28 *mxp++ = 2*sizeof(void *);
29 *(int32_t *)mxp = ptr2addr(J2GG(as->J)->dispatch); mxp += 4;
30 /* Jump to exit handler which fills in the ExitState. */
31 *mxp++ = XI_JMP; mxp += 4;
32 *((int32_t *)(mxp-4)) = jmprel(mxp, (MCode *)(void *)lj_vm_exit_handler);
33 /* Commit the code for this group (even if assembly fails later on). */
34 lj_mcode_commitbot(as->J, mxp);
35 as->mcbot = mxp;
36 as->mclim = as->mcbot + MCLIM_REDZONE;
37 return mxpstart;
38}
39
40/* Setup all needed exit stubs. */
41static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
42{
43 ExitNo i;
44 if (nexits >= EXITSTUBS_PER_GROUP*LJ_MAX_EXITSTUBGR)
45 lj_trace_err(as->J, LJ_TRERR_SNAPOV);
46 for (i = 0; i < (nexits+EXITSTUBS_PER_GROUP-1)/EXITSTUBS_PER_GROUP; i++)
47 if (as->J->exitstubgroup[i] == NULL)
48 as->J->exitstubgroup[i] = asm_exitstub_gen(as, i);
49}
50
51/* Emit conditional branch to exit for guard.
52** It's important to emit this *after* all registers have been allocated,
53** because rematerializations may invalidate the flags.
54*/
55static void asm_guardcc(ASMState *as, int cc)
56{
57 MCode *target = exitstub_addr(as->J, as->snapno);
58 MCode *p = as->mcp;
59 if (LJ_UNLIKELY(p == as->invmcp)) {
60 as->loopinv = 1;
61 *(int32_t *)(p+1) = jmprel(p+5, target);
62 target = p;
63 cc ^= 1;
64 if (as->realign) {
65 emit_sjcc(as, cc, target);
66 return;
67 }
68 }
69 emit_jcc(as, cc, target);
70}
71
72/* -- Memory operand fusion ----------------------------------------------- */
73
74/* Limit linear search to this distance. Avoids O(n^2) behavior. */
75#define CONFLICT_SEARCH_LIM 31
76
77/* Check if a reference is a signed 32 bit constant. */
78static int asm_isk32(ASMState *as, IRRef ref, int32_t *k)
79{
80 if (irref_isk(ref)) {
81 IRIns *ir = IR(ref);
82 if (ir->o != IR_KINT64) {
83 *k = ir->i;
84 return 1;
85 } else if (checki32((int64_t)ir_kint64(ir)->u64)) {
86 *k = (int32_t)ir_kint64(ir)->u64;
87 return 1;
88 }
89 }
90 return 0;
91}
92
93/* Check if there's no conflicting instruction between curins and ref.
94** Also avoid fusing loads if there are multiple references.
95*/
96static int noconflict(ASMState *as, IRRef ref, IROp conflict, int noload)
97{
98 IRIns *ir = as->ir;
99 IRRef i = as->curins;
100 if (i > ref + CONFLICT_SEARCH_LIM)
101 return 0; /* Give up, ref is too far away. */
102 while (--i > ref) {
103 if (ir[i].o == conflict)
104 return 0; /* Conflict found. */
105 else if (!noload && (ir[i].op1 == ref || ir[i].op2 == ref))
106 return 0;
107 }
108 return 1; /* Ok, no conflict. */
109}
110
111/* Fuse array base into memory operand. */
112static IRRef asm_fuseabase(ASMState *as, IRRef ref)
113{
114 IRIns *irb = IR(ref);
115 as->mrm.ofs = 0;
116 if (irb->o == IR_FLOAD) {
117 IRIns *ira = IR(irb->op1);
118 lua_assert(irb->op2 == IRFL_TAB_ARRAY);
119 /* We can avoid the FLOAD of t->array for colocated arrays. */
120 if (ira->o == IR_TNEW && ira->op1 <= LJ_MAX_COLOSIZE &&
121 noconflict(as, irb->op1, IR_NEWREF, 1)) {
122 as->mrm.ofs = (int32_t)sizeof(GCtab); /* Ofs to colocated array. */
123 return irb->op1; /* Table obj. */
124 }
125 } else if (irb->o == IR_ADD && irref_isk(irb->op2)) {
126 /* Fuse base offset (vararg load). */
127 as->mrm.ofs = IR(irb->op2)->i;
128 return irb->op1;
129 }
130 return ref; /* Otherwise use the given array base. */
131}
132
133/* Fuse array reference into memory operand. */
134static void asm_fusearef(ASMState *as, IRIns *ir, RegSet allow)
135{
136 IRIns *irx;
137 lua_assert(ir->o == IR_AREF);
138 as->mrm.base = (uint8_t)ra_alloc1(as, asm_fuseabase(as, ir->op1), allow);
139 irx = IR(ir->op2);
140 if (irref_isk(ir->op2)) {
141 as->mrm.ofs += 8*irx->i;
142 as->mrm.idx = RID_NONE;
143 } else {
144 rset_clear(allow, as->mrm.base);
145 as->mrm.scale = XM_SCALE8;
146 /* Fuse a constant ADD (e.g. t[i+1]) into the offset.
147 ** Doesn't help much without ABCelim, but reduces register pressure.
148 */
149 if (!LJ_64 && /* Has bad effects with negative index on x64. */
150 mayfuse(as, ir->op2) && ra_noreg(irx->r) &&
151 irx->o == IR_ADD && irref_isk(irx->op2)) {
152 as->mrm.ofs += 8*IR(irx->op2)->i;
153 as->mrm.idx = (uint8_t)ra_alloc1(as, irx->op1, allow);
154 } else {
155 as->mrm.idx = (uint8_t)ra_alloc1(as, ir->op2, allow);
156 }
157 }
158}
159
160/* Fuse array/hash/upvalue reference into memory operand.
161** Caveat: this may allocate GPRs for the base/idx registers. Be sure to
162** pass the final allow mask, excluding any GPRs used for other inputs.
163** In particular: 2-operand GPR instructions need to call ra_dest() first!
164*/
165static void asm_fuseahuref(ASMState *as, IRRef ref, RegSet allow)
166{
167 IRIns *ir = IR(ref);
168 if (ra_noreg(ir->r)) {
169 switch ((IROp)ir->o) {
170 case IR_AREF:
171 if (mayfuse(as, ref)) {
172 asm_fusearef(as, ir, allow);
173 return;
174 }
175 break;
176 case IR_HREFK:
177 if (mayfuse(as, ref)) {
178 as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
179 as->mrm.ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
180 as->mrm.idx = RID_NONE;
181 return;
182 }
183 break;
184 case IR_UREFC:
185 if (irref_isk(ir->op1)) {
186 GCfunc *fn = ir_kfunc(IR(ir->op1));
187 GCupval *uv = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv;
188 as->mrm.ofs = ptr2addr(&uv->tv);
189 as->mrm.base = as->mrm.idx = RID_NONE;
190 return;
191 }
192 break;
193 default:
194 lua_assert(ir->o == IR_HREF || ir->o == IR_NEWREF || ir->o == IR_UREFO);
195 break;
196 }
197 }
198 as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
199 as->mrm.ofs = 0;
200 as->mrm.idx = RID_NONE;
201}
202
203/* Fuse FLOAD/FREF reference into memory operand. */
204static void asm_fusefref(ASMState *as, IRIns *ir, RegSet allow)
205{
206 lua_assert(ir->o == IR_FLOAD || ir->o == IR_FREF);
207 as->mrm.ofs = field_ofs[ir->op2];
208 as->mrm.idx = RID_NONE;
209 if (irref_isk(ir->op1)) {
210 as->mrm.ofs += IR(ir->op1)->i;
211 as->mrm.base = RID_NONE;
212 } else {
213 as->mrm.base = (uint8_t)ra_alloc1(as, ir->op1, allow);
214 }
215}
216
217/* Fuse string reference into memory operand. */
218static void asm_fusestrref(ASMState *as, IRIns *ir, RegSet allow)
219{
220 IRIns *irr;
221 lua_assert(ir->o == IR_STRREF);
222 as->mrm.base = as->mrm.idx = RID_NONE;
223 as->mrm.scale = XM_SCALE1;
224 as->mrm.ofs = sizeof(GCstr);
225 if (irref_isk(ir->op1)) {
226 as->mrm.ofs += IR(ir->op1)->i;
227 } else {
228 Reg r = ra_alloc1(as, ir->op1, allow);
229 rset_clear(allow, r);
230 as->mrm.base = (uint8_t)r;
231 }
232 irr = IR(ir->op2);
233 if (irref_isk(ir->op2)) {
234 as->mrm.ofs += irr->i;
235 } else {
236 Reg r;
237 /* Fuse a constant add into the offset, e.g. string.sub(s, i+10). */
238 if (!LJ_64 && /* Has bad effects with negative index on x64. */
239 mayfuse(as, ir->op2) && irr->o == IR_ADD && irref_isk(irr->op2)) {
240 as->mrm.ofs += IR(irr->op2)->i;
241 r = ra_alloc1(as, irr->op1, allow);
242 } else {
243 r = ra_alloc1(as, ir->op2, allow);
244 }
245 if (as->mrm.base == RID_NONE)
246 as->mrm.base = (uint8_t)r;
247 else
248 as->mrm.idx = (uint8_t)r;
249 }
250}
251
252static void asm_fusexref(ASMState *as, IRRef ref, RegSet allow)
253{
254 IRIns *ir = IR(ref);
255 as->mrm.idx = RID_NONE;
256 if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
257 as->mrm.ofs = ir->i;
258 as->mrm.base = RID_NONE;
259 } else if (ir->o == IR_STRREF) {
260 asm_fusestrref(as, ir, allow);
261 } else {
262 as->mrm.ofs = 0;
263 if (canfuse(as, ir) && ir->o == IR_ADD && ra_noreg(ir->r)) {
264 /* Gather (base+idx*sz)+ofs as emitted by cdata ptr/array indexing. */
265 IRIns *irx;
266 IRRef idx;
267 Reg r;
268 if (asm_isk32(as, ir->op2, &as->mrm.ofs)) { /* Recognize x+ofs. */
269 ref = ir->op1;
270 ir = IR(ref);
271 if (!(ir->o == IR_ADD && canfuse(as, ir) && ra_noreg(ir->r)))
272 goto noadd;
273 }
274 as->mrm.scale = XM_SCALE1;
275 idx = ir->op1;
276 ref = ir->op2;
277 irx = IR(idx);
278 if (!(irx->o == IR_BSHL || irx->o == IR_ADD)) { /* Try other operand. */
279 idx = ir->op2;
280 ref = ir->op1;
281 irx = IR(idx);
282 }
283 if (canfuse(as, irx) && ra_noreg(irx->r)) {
284 if (irx->o == IR_BSHL && irref_isk(irx->op2) && IR(irx->op2)->i <= 3) {
285 /* Recognize idx<<b with b = 0-3, corresponding to sz = (1),2,4,8. */
286 idx = irx->op1;
287 as->mrm.scale = (uint8_t)(IR(irx->op2)->i << 6);
288 } else if (irx->o == IR_ADD && irx->op1 == irx->op2) {
289 /* FOLD does idx*2 ==> idx<<1 ==> idx+idx. */
290 idx = irx->op1;
291 as->mrm.scale = XM_SCALE2;
292 }
293 }
294 r = ra_alloc1(as, idx, allow);
295 rset_clear(allow, r);
296 as->mrm.idx = (uint8_t)r;
297 }
298 noadd:
299 as->mrm.base = (uint8_t)ra_alloc1(as, ref, allow);
300 }
301}
302
303/* Fuse load into memory operand. */
304static Reg asm_fuseload(ASMState *as, IRRef ref, RegSet allow)
305{
306 IRIns *ir = IR(ref);
307 if (ra_hasreg(ir->r)) {
308 if (allow != RSET_EMPTY) { /* Fast path. */
309 ra_noweak(as, ir->r);
310 return ir->r;
311 }
312 fusespill:
313 /* Force a spill if only memory operands are allowed (asm_x87load). */
314 as->mrm.base = RID_ESP;
315 as->mrm.ofs = ra_spill(as, ir);
316 as->mrm.idx = RID_NONE;
317 return RID_MRM;
318 }
319 if (ir->o == IR_KNUM) {
320 RegSet avail = as->freeset & ~as->modset & RSET_FPR;
321 lua_assert(allow != RSET_EMPTY);
322 if (!(avail & (avail-1))) { /* Fuse if less than two regs available. */
323 as->mrm.ofs = ptr2addr(ir_knum(ir));
324 as->mrm.base = as->mrm.idx = RID_NONE;
325 return RID_MRM;
326 }
327 } else if (mayfuse(as, ref)) {
328 RegSet xallow = (allow & RSET_GPR) ? allow : RSET_GPR;
329 if (ir->o == IR_SLOAD) {
330 if (!(ir->op2 & (IRSLOAD_PARENT|IRSLOAD_CONVERT)) &&
331 noconflict(as, ref, IR_RETF, 0)) {
332 as->mrm.base = (uint8_t)ra_alloc1(as, REF_BASE, xallow);
333 as->mrm.ofs = 8*((int32_t)ir->op1-1) + ((ir->op2&IRSLOAD_FRAME)?4:0);
334 as->mrm.idx = RID_NONE;
335 return RID_MRM;
336 }
337 } else if (ir->o == IR_FLOAD) {
338 /* Generic fusion is only ok for 32 bit operand (but see asm_comp). */
339 if ((irt_isint(ir->t) || irt_isaddr(ir->t)) &&
340 noconflict(as, ref, IR_FSTORE, 0)) {
341 asm_fusefref(as, ir, xallow);
342 return RID_MRM;
343 }
344 } else if (ir->o == IR_ALOAD || ir->o == IR_HLOAD || ir->o == IR_ULOAD) {
345 if (noconflict(as, ref, ir->o + IRDELTA_L2S, 0)) {
346 asm_fuseahuref(as, ir->op1, xallow);
347 return RID_MRM;
348 }
349 } else if (ir->o == IR_XLOAD) {
350 /* Generic fusion is not ok for 8/16 bit operands (but see asm_comp).
351 ** Fusing unaligned memory operands is ok on x86 (except for SIMD types).
352 */
353 if ((!irt_typerange(ir->t, IRT_I8, IRT_U16)) &&
354 noconflict(as, ref, IR_XSTORE, 0)) {
355 asm_fusexref(as, ir->op1, xallow);
356 return RID_MRM;
357 }
358 } else if (ir->o == IR_VLOAD) {
359 asm_fuseahuref(as, ir->op1, xallow);
360 return RID_MRM;
361 }
362 }
363 if (!(as->freeset & allow) &&
364 (allow == RSET_EMPTY || ra_hasspill(ir->s) || iscrossref(as, ref)))
365 goto fusespill;
366 return ra_allocref(as, ref, allow);
367}
368
369/* -- Calls --------------------------------------------------------------- */
370
371/* Generate a call to a C function. */
372static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
373{
374 uint32_t n, nargs = CCI_NARGS(ci);
375 int32_t ofs = STACKARG_OFS;
376 uint32_t gprs = REGARG_GPRS;
377#if LJ_64
378 Reg fpr = REGARG_FIRSTFPR;
379#endif
380 lua_assert(!(nargs > 2 && (ci->flags&CCI_FASTCALL))); /* Avoid stack adj. */
381 if ((void *)ci->func)
382 emit_call(as, ci->func);
383 for (n = 0; n < nargs; n++) { /* Setup args. */
384 IRRef ref = args[n];
385 IRIns *ir = IR(ref);
386 Reg r;
387#if LJ_64 && LJ_ABI_WIN
388 /* Windows/x64 argument registers are strictly positional. */
389 r = irt_isfp(ir->t) ? (fpr <= REGARG_LASTFPR ? fpr : 0) : (gprs & 31);
390 fpr++; gprs >>= 5;
391#elif LJ_64
392 /* POSIX/x64 argument registers are used in order of appearance. */
393 if (irt_isfp(ir->t)) {
394 r = fpr <= REGARG_LASTFPR ? fpr : 0; fpr++;
395 } else {
396 r = gprs & 31; gprs >>= 5;
397 }
398#else
399 if (irt_isfp(ir->t) || !(ci->flags & CCI_FASTCALL)) {
400 r = 0;
401 } else {
402 r = gprs & 31; gprs >>= 5;
403 }
404#endif
405 if (r) { /* Argument is in a register. */
406 if (r < RID_MAX_GPR && ref < ASMREF_TMP1) {
407#if LJ_64
408 if (ir->o == IR_KINT64)
409 emit_loadu64(as, r, ir_kint64(ir)->u64);
410 else
411#endif
412 emit_loadi(as, r, ir->i);
413 } else {
414 lua_assert(rset_test(as->freeset, r)); /* Must have been evicted. */
415 if (ra_hasreg(ir->r)) {
416 ra_noweak(as, ir->r);
417 emit_movrr(as, ir, r, ir->r);
418 } else {
419 ra_allocref(as, ref, RID2RSET(r));
420 }
421 }
422 } else if (irt_isfp(ir->t)) { /* FP argument is on stack. */
423 lua_assert(!(irt_isfloat(ir->t) && irref_isk(ref))); /* No float k. */
424 if (LJ_32 && (ofs & 4) && irref_isk(ref)) {
425 /* Split stores for unaligned FP consts. */
426 emit_movmroi(as, RID_ESP, ofs, (int32_t)ir_knum(ir)->u32.lo);
427 emit_movmroi(as, RID_ESP, ofs+4, (int32_t)ir_knum(ir)->u32.hi);
428 } else {
429 r = ra_alloc1(as, ref, RSET_FPR);
430 emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto,
431 r, RID_ESP, ofs);
432 }
433 ofs += (LJ_32 && irt_isfloat(ir->t)) ? 4 : 8;
434 } else { /* Non-FP argument is on stack. */
435 if (LJ_32 && ref < ASMREF_TMP1) {
436 emit_movmroi(as, RID_ESP, ofs, ir->i);
437 } else {
438 r = ra_alloc1(as, ref, RSET_GPR);
439 emit_movtomro(as, REX_64IR(ir, r), RID_ESP, ofs);
440 }
441 ofs += sizeof(intptr_t);
442 }
443 }
444}
445
446/* Setup result reg/sp for call. Evict scratch regs. */
447static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
448{
449 RegSet drop = RSET_SCRATCH;
450 if ((ci->flags & CCI_NOFPRCLOBBER))
451 drop &= ~RSET_FPR;
452 if (ra_hasreg(ir->r))
453 rset_clear(drop, ir->r); /* Dest reg handled below. */
454 ra_evictset(as, drop); /* Evictions must be performed first. */
455 if (ra_used(ir)) {
456 if (irt_isfp(ir->t)) {
457 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
458#if LJ_64
459 if ((ci->flags & CCI_CASTU64)) {
460 Reg dest = ir->r;
461 if (ra_hasreg(dest)) {
462 ra_free(as, dest);
463 ra_modified(as, dest);
464 emit_rr(as, XO_MOVD, dest|REX_64, RID_RET); /* Really MOVQ. */
465 } else {
466 emit_movtomro(as, RID_RET|REX_64, RID_ESP, ofs);
467 }
468 } else {
469 ra_destreg(as, ir, RID_FPRET);
470 }
471#else
472 /* Number result is in x87 st0 for x86 calling convention. */
473 Reg dest = ir->r;
474 if (ra_hasreg(dest)) {
475 ra_free(as, dest);
476 ra_modified(as, dest);
477 emit_rmro(as, irt_isnum(ir->t) ? XMM_MOVRM(as) : XO_MOVSS,
478 dest, RID_ESP, ofs);
479 }
480 if ((ci->flags & CCI_CASTU64)) {
481 emit_movtomro(as, RID_RET, RID_ESP, ofs);
482 emit_movtomro(as, RID_RETHI, RID_ESP, ofs+4);
483 } else {
484 emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
485 irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
486 }
487#endif
488 } else {
489 lua_assert(!irt_ispri(ir->t));
490 ra_destreg(as, ir, RID_RET);
491 }
492 } else if (LJ_32 && irt_isfp(ir->t)) {
493 emit_x87op(as, XI_FPOP); /* Pop unused result from x87 st0. */
494 }
495}
496
497static void asm_call(ASMState *as, IRIns *ir)
498{
499 IRRef args[CCI_NARGS_MAX];
500 const CCallInfo *ci = &lj_ir_callinfo[ir->op2];
501 asm_collectargs(as, ir, ci, args);
502 asm_setupresult(as, ir, ci);
503 asm_gencall(as, ci, args);
504}
505
506static void asm_callx(ASMState *as, IRIns *ir)
507{
508 IRRef args[CCI_NARGS_MAX];
509 CCallInfo ci;
510 IRIns *irf;
511 ci.flags = asm_callx_flags(as, ir);
512 asm_collectargs(as, ir, &ci, args);
513 asm_setupresult(as, ir, &ci);
514 irf = IR(ir->op2);
515 if (LJ_32 && irref_isk(ir->op2)) { /* Call to constant address on x86. */
516 ci.func = (ASMFunction)(void *)(uintptr_t)(uint32_t)irf->i;
517 } else {
518 /* Prefer a non-argument register or RID_RET for indirect calls. */
519 RegSet allow = (RSET_GPR & ~RSET_SCRATCH)|RID2RSET(RID_RET);
520 Reg r = ra_alloc1(as, ir->op2, allow);
521 emit_rr(as, XO_GROUP5, XOg_CALL, r);
522 ci.func = (ASMFunction)(void *)0;
523 }
524 asm_gencall(as, &ci, args);
525}
526
527/* -- Returns ------------------------------------------------------------- */
528
529/* Return to lower frame. Guard that it goes to the right spot. */
530static void asm_retf(ASMState *as, IRIns *ir)
531{
532 Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
533 void *pc = ir_kptr(IR(ir->op2));
534 int32_t delta = 1+bc_a(*((const BCIns *)pc - 1));
535 as->topslot -= (BCReg)delta;
536 if ((int32_t)as->topslot < 0) as->topslot = 0;
537 emit_setgl(as, base, jit_base);
538 emit_addptr(as, base, -8*delta);
539 asm_guardcc(as, CC_NE);
540 emit_gmroi(as, XG_ARITHi(XOg_CMP), base, -4, ptr2addr(pc));
541}
542
543/* -- Type conversions ---------------------------------------------------- */
544
545static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
546{
547 Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
548 Reg dest = ra_dest(as, ir, RSET_GPR);
549 asm_guardcc(as, CC_P);
550 asm_guardcc(as, CC_NE);
551 emit_rr(as, XO_UCOMISD, left, tmp);
552 emit_rr(as, XO_CVTSI2SD, tmp, dest);
553 if (!(as->flags & JIT_F_SPLIT_XMM))
554 emit_rr(as, XO_XORPS, tmp, tmp); /* Avoid partial register stall. */
555 emit_rr(as, XO_CVTTSD2SI, dest, left);
556 /* Can't fuse since left is needed twice. */
557}
558
559static void asm_tobit(ASMState *as, IRIns *ir)
560{
561 Reg dest = ra_dest(as, ir, RSET_GPR);
562 Reg tmp = ra_noreg(IR(ir->op1)->r) ?
563 ra_alloc1(as, ir->op1, RSET_FPR) :
564 ra_scratch(as, RSET_FPR);
565 Reg right = asm_fuseload(as, ir->op2, rset_exclude(RSET_FPR, tmp));
566 emit_rr(as, XO_MOVDto, tmp, dest);
567 emit_mrm(as, XO_ADDSD, tmp, right);
568 ra_left(as, tmp, ir->op1);
569}
570
571static void asm_conv(ASMState *as, IRIns *ir)
572{
573 IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
574 int st64 = (st == IRT_I64 || st == IRT_U64 || (LJ_64 && st == IRT_P64));
575 int stfp = (st == IRT_NUM || st == IRT_FLOAT);
576 IRRef lref = ir->op1;
577 lua_assert(irt_type(ir->t) != st);
578 lua_assert(!(LJ_32 && (irt_isint64(ir->t) || st64))); /* Handled by SPLIT. */
579 if (irt_isfp(ir->t)) {
580 Reg dest = ra_dest(as, ir, RSET_FPR);
581 if (stfp) { /* FP to FP conversion. */
582 Reg left = asm_fuseload(as, lref, RSET_FPR);
583 emit_mrm(as, st == IRT_NUM ? XO_CVTSD2SS : XO_CVTSS2SD, dest, left);
584 if (left == dest) return; /* Avoid the XO_XORPS. */
585 } else if (LJ_32 && st == IRT_U32) { /* U32 to FP conversion on x86. */
586 /* number = (2^52+2^51 .. u32) - (2^52+2^51) */
587 cTValue *k = lj_ir_k64_find(as->J, U64x(43380000,00000000));
588 Reg bias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
589 if (irt_isfloat(ir->t))
590 emit_rr(as, XO_CVTSD2SS, dest, dest);
591 emit_rr(as, XO_SUBSD, dest, bias); /* Subtract 2^52+2^51 bias. */
592 emit_rr(as, XO_XORPS, dest, bias); /* Merge bias and integer. */
593 emit_loadn(as, bias, k);
594 emit_mrm(as, XO_MOVD, dest, asm_fuseload(as, lref, RSET_GPR));
595 return;
596 } else { /* Integer to FP conversion. */
597 Reg left = (LJ_64 && (st == IRT_U32 || st == IRT_U64)) ?
598 ra_alloc1(as, lref, RSET_GPR) :
599 asm_fuseload(as, lref, RSET_GPR);
600 if (LJ_64 && st == IRT_U64) {
601 MCLabel l_end = emit_label(as);
602 const void *k = lj_ir_k64_find(as->J, U64x(43f00000,00000000));
603 emit_rma(as, XO_ADDSD, dest, k); /* Add 2^64 to compensate. */
604 emit_sjcc(as, CC_NS, l_end);
605 emit_rr(as, XO_TEST, left|REX_64, left); /* Check if u64 >= 2^63. */
606 }
607 emit_mrm(as, irt_isnum(ir->t) ? XO_CVTSI2SD : XO_CVTSI2SS,
608 dest|((LJ_64 && (st64 || st == IRT_U32)) ? REX_64 : 0), left);
609 }
610 if (!(as->flags & JIT_F_SPLIT_XMM))
611 emit_rr(as, XO_XORPS, dest, dest); /* Avoid partial register stall. */
612 } else if (stfp) { /* FP to integer conversion. */
613 if (irt_isguard(ir->t)) {
614 /* Checked conversions are only supported from number to int. */
615 lua_assert(irt_isint(ir->t) && st == IRT_NUM);
616 asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
617 } else {
618 Reg dest = ra_dest(as, ir, RSET_GPR);
619 x86Op op = st == IRT_NUM ?
620 ((ir->op2 & IRCONV_TRUNC) ? XO_CVTTSD2SI : XO_CVTSD2SI) :
621 ((ir->op2 & IRCONV_TRUNC) ? XO_CVTTSS2SI : XO_CVTSS2SI);
622 if (LJ_32 && irt_isu32(ir->t)) { /* FP to U32 conversion on x86. */
623 /* u32 = (int32_t)(number - 2^31) + 2^31 */
624 Reg tmp = ra_noreg(IR(lref)->r) ? ra_alloc1(as, lref, RSET_FPR) :
625 ra_scratch(as, RSET_FPR);
626 emit_gri(as, XG_ARITHi(XOg_ADD), dest, (int32_t)0x80000000);
627 emit_rr(as, op, dest, tmp);
628 if (st == IRT_NUM)
629 emit_rma(as, XO_ADDSD, tmp,
630 lj_ir_k64_find(as->J, U64x(c1e00000,00000000)));
631 else
632 emit_rma(as, XO_ADDSS, tmp,
633 lj_ir_k64_find(as->J, U64x(00000000,cf000000)));
634 ra_left(as, tmp, lref);
635 } else if (LJ_64 && irt_isu64(ir->t)) {
636 /* For inputs in [2^63,2^64-1] add -2^64 and convert again. */
637 Reg tmp = ra_noreg(IR(lref)->r) ? ra_alloc1(as, lref, RSET_FPR) :
638 ra_scratch(as, RSET_FPR);
639 MCLabel l_end = emit_label(as);
640 emit_rr(as, op, dest|REX_64, tmp);
641 if (st == IRT_NUM)
642 emit_rma(as, XO_ADDSD, tmp,
643 lj_ir_k64_find(as->J, U64x(c3f00000,00000000)));
644 else
645 emit_rma(as, XO_ADDSS, tmp,
646 lj_ir_k64_find(as->J, U64x(00000000,df800000)));
647 emit_sjcc(as, CC_NS, l_end);
648 emit_rr(as, XO_TEST, dest|REX_64, dest); /* Check if dest < 2^63. */
649 emit_rr(as, op, dest|REX_64, tmp);
650 ra_left(as, tmp, lref);
651 } else {
652 Reg left = asm_fuseload(as, lref, RSET_FPR);
653 if (LJ_64 && irt_isu32(ir->t))
654 emit_rr(as, XO_MOV, dest, dest); /* Zero hiword. */
655 emit_mrm(as, op,
656 dest|((LJ_64 &&
657 (irt_is64(ir->t) || irt_isu32(ir->t))) ? REX_64 : 0),
658 left);
659 }
660 }
661 } else if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
662 Reg left, dest = ra_dest(as, ir, RSET_GPR);
663 RegSet allow = RSET_GPR;
664 x86Op op;
665 lua_assert(irt_isint(ir->t) || irt_isu32(ir->t));
666 if (st == IRT_I8) {
667 op = XO_MOVSXb; allow = RSET_GPR8; dest |= FORCE_REX;
668 } else if (st == IRT_U8) {
669 op = XO_MOVZXb; allow = RSET_GPR8; dest |= FORCE_REX;
670 } else if (st == IRT_I16) {
671 op = XO_MOVSXw;
672 } else {
673 op = XO_MOVZXw;
674 }
675 left = asm_fuseload(as, lref, allow);
676 /* Add extra MOV if source is already in wrong register. */
677 if (!LJ_64 && left != RID_MRM && !rset_test(allow, left)) {
678 Reg tmp = ra_scratch(as, allow);
679 emit_rr(as, op, dest, tmp);
680 emit_rr(as, XO_MOV, tmp, left);
681 } else {
682 emit_mrm(as, op, dest, left);
683 }
684 } else { /* 32/64 bit integer conversions. */
685 if (LJ_32) { /* Only need to handle 32/32 bit no-op (cast) on x86. */
686 Reg dest = ra_dest(as, ir, RSET_GPR);
687 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
688 } else if (irt_is64(ir->t)) {
689 Reg dest = ra_dest(as, ir, RSET_GPR);
690 if (st64 || !(ir->op2 & IRCONV_SEXT)) {
691 /* 64/64 bit no-op (cast) or 32 to 64 bit zero extension. */
692 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
693 } else { /* 32 to 64 bit sign extension. */
694 Reg left = asm_fuseload(as, lref, RSET_GPR);
695 emit_mrm(as, XO_MOVSXd, dest|REX_64, left);
696 }
697 } else {
698 Reg dest = ra_dest(as, ir, RSET_GPR);
699 if (st64) {
700 Reg left = asm_fuseload(as, lref, RSET_GPR);
701 /* This is either a 32 bit reg/reg mov which zeroes the hiword
702 ** or a load of the loword from a 64 bit address.
703 */
704 emit_mrm(as, XO_MOV, dest, left);
705 } else { /* 32/32 bit no-op (cast). */
706 ra_left(as, dest, lref); /* Do nothing, but may need to move regs. */
707 }
708 }
709 }
710}
711
712#if LJ_32 && LJ_HASFFI
713/* No SSE conversions to/from 64 bit on x86, so resort to ugly x87 code. */
714
715/* 64 bit integer to FP conversion in 32 bit mode. */
716static void asm_conv_fp_int64(ASMState *as, IRIns *ir)
717{
718 Reg hi = ra_alloc1(as, ir->op1, RSET_GPR);
719 Reg lo = ra_alloc1(as, (ir-1)->op1, rset_exclude(RSET_GPR, hi));
720 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
721 Reg dest = ir->r;
722 if (ra_hasreg(dest)) {
723 ra_free(as, dest);
724 ra_modified(as, dest);
725 emit_rmro(as, irt_isnum(ir->t) ? XMM_MOVRM(as) : XO_MOVSS,
726 dest, RID_ESP, ofs);
727 }
728 emit_rmro(as, irt_isnum(ir->t) ? XO_FSTPq : XO_FSTPd,
729 irt_isnum(ir->t) ? XOg_FSTPq : XOg_FSTPd, RID_ESP, ofs);
730 if (((ir-1)->op2 & IRCONV_SRCMASK) == IRT_U64) {
731 /* For inputs in [2^63,2^64-1] add 2^64 to compensate. */
732 MCLabel l_end = emit_label(as);
733 emit_rma(as, XO_FADDq, XOg_FADDq,
734 lj_ir_k64_find(as->J, U64x(43f00000,00000000)));
735 emit_sjcc(as, CC_NS, l_end);
736 emit_rr(as, XO_TEST, hi, hi); /* Check if u64 >= 2^63. */
737 } else {
738 lua_assert(((ir-1)->op2 & IRCONV_SRCMASK) == IRT_I64);
739 }
740 emit_rmro(as, XO_FILDq, XOg_FILDq, RID_ESP, 0);
741 /* NYI: Avoid narrow-to-wide store-to-load forwarding stall. */
742 emit_rmro(as, XO_MOVto, hi, RID_ESP, 4);
743 emit_rmro(as, XO_MOVto, lo, RID_ESP, 0);
744}
745
746/* FP to 64 bit integer conversion in 32 bit mode. */
747static void asm_conv_int64_fp(ASMState *as, IRIns *ir)
748{
749 IRType st = (IRType)((ir-1)->op2 & IRCONV_SRCMASK);
750 IRType dt = (((ir-1)->op2 & IRCONV_DSTMASK) >> IRCONV_DSH);
751 Reg lo, hi;
752 lua_assert(st == IRT_NUM || st == IRT_FLOAT);
753 lua_assert(dt == IRT_I64 || dt == IRT_U64);
754 lua_assert(((ir-1)->op2 & IRCONV_TRUNC));
755 hi = ra_dest(as, ir, RSET_GPR);
756 lo = ra_dest(as, ir-1, rset_exclude(RSET_GPR, hi));
757 if (ra_used(ir-1)) emit_rmro(as, XO_MOV, lo, RID_ESP, 0);
758 /* NYI: Avoid wide-to-narrow store-to-load forwarding stall. */
759 if (!(as->flags & JIT_F_SSE3)) { /* Set FPU rounding mode to default. */
760 emit_rmro(as, XO_FLDCW, XOg_FLDCW, RID_ESP, 4);
761 emit_rmro(as, XO_MOVto, lo, RID_ESP, 4);
762 emit_gri(as, XG_ARITHi(XOg_AND), lo, 0xf3ff);
763 }
764 if (dt == IRT_U64) {
765 /* For inputs in [2^63,2^64-1] add -2^64 and convert again. */
766 MCLabel l_pop, l_end = emit_label(as);
767 emit_x87op(as, XI_FPOP);
768 l_pop = emit_label(as);
769 emit_sjmp(as, l_end);
770 emit_rmro(as, XO_MOV, hi, RID_ESP, 4);
771 if ((as->flags & JIT_F_SSE3))
772 emit_rmro(as, XO_FISTTPq, XOg_FISTTPq, RID_ESP, 0);
773 else
774 emit_rmro(as, XO_FISTPq, XOg_FISTPq, RID_ESP, 0);
775 emit_rma(as, XO_FADDq, XOg_FADDq,
776 lj_ir_k64_find(as->J, U64x(c3f00000,00000000)));
777 emit_sjcc(as, CC_NS, l_pop);
778 emit_rr(as, XO_TEST, hi, hi); /* Check if out-of-range (2^63). */
779 }
780 emit_rmro(as, XO_MOV, hi, RID_ESP, 4);
781 if ((as->flags & JIT_F_SSE3)) { /* Truncation is easy with SSE3. */
782 emit_rmro(as, XO_FISTTPq, XOg_FISTTPq, RID_ESP, 0);
783 } else { /* Otherwise set FPU rounding mode to truncate before the store. */
784 emit_rmro(as, XO_FISTPq, XOg_FISTPq, RID_ESP, 0);
785 emit_rmro(as, XO_FLDCW, XOg_FLDCW, RID_ESP, 0);
786 emit_rmro(as, XO_MOVtow, lo, RID_ESP, 0);
787 emit_rmro(as, XO_ARITHw(XOg_OR), lo, RID_ESP, 0);
788 emit_loadi(as, lo, 0xc00);
789 emit_rmro(as, XO_FNSTCW, XOg_FNSTCW, RID_ESP, 0);
790 }
791 if (dt == IRT_U64)
792 emit_x87op(as, XI_FDUP);
793 emit_mrm(as, st == IRT_NUM ? XO_FLDq : XO_FLDd,
794 st == IRT_NUM ? XOg_FLDq: XOg_FLDd,
795 asm_fuseload(as, ir->op1, RSET_EMPTY));
796}
797#endif
798
799static void asm_strto(ASMState *as, IRIns *ir)
800{
801 /* Force a spill slot for the destination register (if any). */
802 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_str_tonum];
803 IRRef args[2];
804 RegSet drop = RSET_SCRATCH;
805 if ((drop & RSET_FPR) != RSET_FPR && ra_hasreg(ir->r))
806 rset_set(drop, ir->r); /* WIN64 doesn't spill all FPRs. */
807 ra_evictset(as, drop);
808 asm_guardcc(as, CC_E);
809 emit_rr(as, XO_TEST, RID_RET, RID_RET); /* Test return status. */
810 args[0] = ir->op1; /* GCstr *str */
811 args[1] = ASMREF_TMP1; /* TValue *n */
812 asm_gencall(as, ci, args);
813 /* Store the result to the spill slot or temp slots. */
814 emit_rmro(as, XO_LEA, ra_releasetmp(as, ASMREF_TMP1)|REX_64,
815 RID_ESP, sps_scale(ir->s));
816}
817
818static void asm_tostr(ASMState *as, IRIns *ir)
819{
820 IRIns *irl = IR(ir->op1);
821 IRRef args[2];
822 args[0] = ASMREF_L;
823 as->gcsteps++;
824 if (irt_isnum(irl->t)) {
825 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_str_fromnum];
826 args[1] = ASMREF_TMP1; /* const lua_Number * */
827 asm_setupresult(as, ir, ci); /* GCstr * */
828 asm_gencall(as, ci, args);
829 emit_rmro(as, XO_LEA, ra_releasetmp(as, ASMREF_TMP1)|REX_64,
830 RID_ESP, ra_spill(as, irl));
831 } else {
832 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_str_fromint];
833 args[1] = ir->op1; /* int32_t k */
834 asm_setupresult(as, ir, ci); /* GCstr * */
835 asm_gencall(as, ci, args);
836 }
837}
838
839/* -- Memory references --------------------------------------------------- */
840
841static void asm_aref(ASMState *as, IRIns *ir)
842{
843 Reg dest = ra_dest(as, ir, RSET_GPR);
844 asm_fusearef(as, ir, RSET_GPR);
845 if (!(as->mrm.idx == RID_NONE && as->mrm.ofs == 0))
846 emit_mrm(as, XO_LEA, dest, RID_MRM);
847 else if (as->mrm.base != dest)
848 emit_rr(as, XO_MOV, dest, as->mrm.base);
849}
850
851/* Merge NE(HREF, niltv) check. */
852static MCode *merge_href_niltv(ASMState *as, IRIns *ir)
853{
854 /* Assumes nothing else generates NE of HREF. */
855 if ((ir[1].o == IR_NE || ir[1].o == IR_EQ) && ir[1].op1 == as->curins &&
856 ra_hasreg(ir->r)) {
857 MCode *p = as->mcp;
858 p += (LJ_64 && *p != XI_ARITHi) ? 7+6 : 6+6;
859 /* Ensure no loop branch inversion happened. */
860 if (p[-6] == 0x0f && p[-5] == XI_JCCn+(CC_NE^(ir[1].o & 1))) {
861 as->mcp = p; /* Kill cmp reg, imm32 + jz exit. */
862 return p + *(int32_t *)(p-4); /* Return exit address. */
863 }
864 }
865 return NULL;
866}
867
868/* Inlined hash lookup. Specialized for key type and for const keys.
869** The equivalent C code is:
870** Node *n = hashkey(t, key);
871** do {
872** if (lj_obj_equal(&n->key, key)) return &n->val;
873** } while ((n = nextnode(n)));
874** return niltv(L);
875*/
876static void asm_href(ASMState *as, IRIns *ir)
877{
878 MCode *nilexit = merge_href_niltv(as, ir); /* Do this before any restores. */
879 RegSet allow = RSET_GPR;
880 Reg dest = ra_dest(as, ir, allow);
881 Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
882 Reg key = RID_NONE, tmp = RID_NONE;
883 IRIns *irkey = IR(ir->op2);
884 int isk = irref_isk(ir->op2);
885 IRType1 kt = irkey->t;
886 uint32_t khash;
887 MCLabel l_end, l_loop, l_next;
888
889 if (!isk) {
890 rset_clear(allow, tab);
891 key = ra_alloc1(as, ir->op2, irt_isnum(kt) ? RSET_FPR : allow);
892 if (!irt_isstr(kt))
893 tmp = ra_scratch(as, rset_exclude(allow, key));
894 }
895
896 /* Key not found in chain: jump to exit (if merged with NE) or load niltv. */
897 l_end = emit_label(as);
898 if (nilexit && ir[1].o == IR_NE) {
899 emit_jcc(as, CC_E, nilexit); /* XI_JMP is not found by lj_asm_patchexit. */
900 nilexit = NULL;
901 } else {
902 emit_loada(as, dest, niltvg(J2G(as->J)));
903 }
904
905 /* Follow hash chain until the end. */
906 l_loop = emit_sjcc_label(as, CC_NZ);
907 emit_rr(as, XO_TEST, dest, dest);
908 emit_rmro(as, XO_MOV, dest, dest, offsetof(Node, next));
909 l_next = emit_label(as);
910
911 /* Type and value comparison. */
912 if (nilexit)
913 emit_jcc(as, CC_E, nilexit);
914 else
915 emit_sjcc(as, CC_E, l_end);
916 if (irt_isnum(kt)) {
917 if (isk) {
918 /* Assumes -0.0 is already canonicalized to +0.0. */
919 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.lo),
920 (int32_t)ir_knum(irkey)->u32.lo);
921 emit_sjcc(as, CC_NE, l_next);
922 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.u32.hi),
923 (int32_t)ir_knum(irkey)->u32.hi);
924 } else {
925 emit_sjcc(as, CC_P, l_next);
926 emit_rmro(as, XO_UCOMISD, key, dest, offsetof(Node, key.n));
927 emit_sjcc(as, CC_AE, l_next);
928 /* The type check avoids NaN penalties and complaints from Valgrind. */
929#if LJ_64
930 emit_u32(as, LJ_TISNUM);
931 emit_rmro(as, XO_ARITHi, XOg_CMP, dest, offsetof(Node, key.it));
932#else
933 emit_i8(as, LJ_TISNUM);
934 emit_rmro(as, XO_ARITHi8, XOg_CMP, dest, offsetof(Node, key.it));
935#endif
936 }
937#if LJ_64
938 } else if (irt_islightud(kt)) {
939 emit_rmro(as, XO_CMP, key|REX_64, dest, offsetof(Node, key.u64));
940#endif
941 } else {
942 if (!irt_ispri(kt)) {
943 lua_assert(irt_isaddr(kt));
944 if (isk)
945 emit_gmroi(as, XG_ARITHi(XOg_CMP), dest, offsetof(Node, key.gcr),
946 ptr2addr(ir_kgc(irkey)));
947 else
948 emit_rmro(as, XO_CMP, key, dest, offsetof(Node, key.gcr));
949 emit_sjcc(as, CC_NE, l_next);
950 }
951 lua_assert(!irt_isnil(kt));
952 emit_i8(as, irt_toitype(kt));
953 emit_rmro(as, XO_ARITHi8, XOg_CMP, dest, offsetof(Node, key.it));
954 }
955 emit_sfixup(as, l_loop);
956 checkmclim(as);
957
958 /* Load main position relative to tab->node into dest. */
959 khash = isk ? ir_khash(irkey) : 1;
960 if (khash == 0) {
961 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, node));
962 } else {
963 emit_rmro(as, XO_ARITH(XOg_ADD), dest, tab, offsetof(GCtab, node));
964 if ((as->flags & JIT_F_PREFER_IMUL)) {
965 emit_i8(as, sizeof(Node));
966 emit_rr(as, XO_IMULi8, dest, dest);
967 } else {
968 emit_shifti(as, XOg_SHL, dest, 3);
969 emit_rmrxo(as, XO_LEA, dest, dest, dest, XM_SCALE2, 0);
970 }
971 if (isk) {
972 emit_gri(as, XG_ARITHi(XOg_AND), dest, (int32_t)khash);
973 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, hmask));
974 } else if (irt_isstr(kt)) {
975 emit_rmro(as, XO_ARITH(XOg_AND), dest, key, offsetof(GCstr, hash));
976 emit_rmro(as, XO_MOV, dest, tab, offsetof(GCtab, hmask));
977 } else { /* Must match with hashrot() in lj_tab.c. */
978 emit_rmro(as, XO_ARITH(XOg_AND), dest, tab, offsetof(GCtab, hmask));
979 emit_rr(as, XO_ARITH(XOg_SUB), dest, tmp);
980 emit_shifti(as, XOg_ROL, tmp, HASH_ROT3);
981 emit_rr(as, XO_ARITH(XOg_XOR), dest, tmp);
982 emit_shifti(as, XOg_ROL, dest, HASH_ROT2);
983 emit_rr(as, XO_ARITH(XOg_SUB), tmp, dest);
984 emit_shifti(as, XOg_ROL, dest, HASH_ROT1);
985 emit_rr(as, XO_ARITH(XOg_XOR), tmp, dest);
986 if (irt_isnum(kt)) {
987 emit_rr(as, XO_ARITH(XOg_ADD), dest, dest);
988#if LJ_64
989 emit_shifti(as, XOg_SHR|REX_64, dest, 32);
990 emit_rr(as, XO_MOV, tmp, dest);
991 emit_rr(as, XO_MOVDto, key|REX_64, dest);
992#else
993 emit_rmro(as, XO_MOV, dest, RID_ESP, ra_spill(as, irkey)+4);
994 emit_rr(as, XO_MOVDto, key, tmp);
995#endif
996 } else {
997 emit_rr(as, XO_MOV, tmp, key);
998 emit_rmro(as, XO_LEA, dest, key, HASH_BIAS);
999 }
1000 }
1001 }
1002}
1003
1004static void asm_hrefk(ASMState *as, IRIns *ir)
1005{
1006 IRIns *kslot = IR(ir->op2);
1007 IRIns *irkey = IR(kslot->op1);
1008 int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
1009 Reg dest = ra_used(ir) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
1010 Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
1011#if !LJ_64
1012 MCLabel l_exit;
1013#endif
1014 lua_assert(ofs % sizeof(Node) == 0);
1015 if (ra_hasreg(dest)) {
1016 if (ofs != 0) {
1017 if (dest == node && !(as->flags & JIT_F_LEA_AGU))
1018 emit_gri(as, XG_ARITHi(XOg_ADD), dest, ofs);
1019 else
1020 emit_rmro(as, XO_LEA, dest, node, ofs);
1021 } else if (dest != node) {
1022 emit_rr(as, XO_MOV, dest, node);
1023 }
1024 }
1025 asm_guardcc(as, CC_NE);
1026#if LJ_64
1027 if (!irt_ispri(irkey->t)) {
1028 Reg key = ra_scratch(as, rset_exclude(RSET_GPR, node));
1029 emit_rmro(as, XO_CMP, key|REX_64, node,
1030 ofs + (int32_t)offsetof(Node, key.u64));
1031 lua_assert(irt_isnum(irkey->t) || irt_isgcv(irkey->t));
1032 /* Assumes -0.0 is already canonicalized to +0.0. */
1033 emit_loadu64(as, key, irt_isnum(irkey->t) ? ir_knum(irkey)->u64 :
1034 ((uint64_t)irt_toitype(irkey->t) << 32) |
1035 (uint64_t)(uint32_t)ptr2addr(ir_kgc(irkey)));
1036 } else {
1037 lua_assert(!irt_isnil(irkey->t));
1038 emit_i8(as, irt_toitype(irkey->t));
1039 emit_rmro(as, XO_ARITHi8, XOg_CMP, node,
1040 ofs + (int32_t)offsetof(Node, key.it));
1041 }
1042#else
1043 l_exit = emit_label(as);
1044 if (irt_isnum(irkey->t)) {
1045 /* Assumes -0.0 is already canonicalized to +0.0. */
1046 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1047 ofs + (int32_t)offsetof(Node, key.u32.lo),
1048 (int32_t)ir_knum(irkey)->u32.lo);
1049 emit_sjcc(as, CC_NE, l_exit);
1050 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1051 ofs + (int32_t)offsetof(Node, key.u32.hi),
1052 (int32_t)ir_knum(irkey)->u32.hi);
1053 } else {
1054 if (!irt_ispri(irkey->t)) {
1055 lua_assert(irt_isgcv(irkey->t));
1056 emit_gmroi(as, XG_ARITHi(XOg_CMP), node,
1057 ofs + (int32_t)offsetof(Node, key.gcr),
1058 ptr2addr(ir_kgc(irkey)));
1059 emit_sjcc(as, CC_NE, l_exit);
1060 }
1061 lua_assert(!irt_isnil(irkey->t));
1062 emit_i8(as, irt_toitype(irkey->t));
1063 emit_rmro(as, XO_ARITHi8, XOg_CMP, node,
1064 ofs + (int32_t)offsetof(Node, key.it));
1065 }
1066#endif
1067}
1068
1069static void asm_newref(ASMState *as, IRIns *ir)
1070{
1071 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_tab_newkey];
1072 IRRef args[3];
1073 IRIns *irkey;
1074 Reg tmp;
1075 args[0] = ASMREF_L; /* lua_State *L */
1076 args[1] = ir->op1; /* GCtab *t */
1077 args[2] = ASMREF_TMP1; /* cTValue *key */
1078 asm_setupresult(as, ir, ci); /* TValue * */
1079 asm_gencall(as, ci, args);
1080 tmp = ra_releasetmp(as, ASMREF_TMP1);
1081 irkey = IR(ir->op2);
1082 if (irt_isnum(irkey->t)) {
1083 /* For numbers use the constant itself or a spill slot as a TValue. */
1084 if (irref_isk(ir->op2))
1085 emit_loada(as, tmp, ir_knum(irkey));
1086 else
1087 emit_rmro(as, XO_LEA, tmp|REX_64, RID_ESP, ra_spill(as, irkey));
1088 } else {
1089 /* Otherwise use g->tmptv to hold the TValue. */
1090 if (!irref_isk(ir->op2)) {
1091 Reg src = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, tmp));
1092 emit_movtomro(as, REX_64IR(irkey, src), tmp, 0);
1093 } else if (!irt_ispri(irkey->t)) {
1094 emit_movmroi(as, tmp, 0, irkey->i);
1095 }
1096 if (!(LJ_64 && irt_islightud(irkey->t)))
1097 emit_movmroi(as, tmp, 4, irt_toitype(irkey->t));
1098 emit_loada(as, tmp, &J2G(as->J)->tmptv);
1099 }
1100}
1101
1102static void asm_uref(ASMState *as, IRIns *ir)
1103{
1104 /* NYI: Check that UREFO is still open and not aliasing a slot. */
1105 Reg dest = ra_dest(as, ir, RSET_GPR);
1106 if (irref_isk(ir->op1)) {
1107 GCfunc *fn = ir_kfunc(IR(ir->op1));
1108 MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
1109 emit_rma(as, XO_MOV, dest, v);
1110 } else {
1111 Reg uv = ra_scratch(as, RSET_GPR);
1112 Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
1113 if (ir->o == IR_UREFC) {
1114 emit_rmro(as, XO_LEA, dest, uv, offsetof(GCupval, tv));
1115 asm_guardcc(as, CC_NE);
1116 emit_i8(as, 1);
1117 emit_rmro(as, XO_ARITHib, XOg_CMP, uv, offsetof(GCupval, closed));
1118 } else {
1119 emit_rmro(as, XO_MOV, dest, uv, offsetof(GCupval, v));
1120 }
1121 emit_rmro(as, XO_MOV, uv, func,
1122 (int32_t)offsetof(GCfuncL, uvptr) + 4*(int32_t)(ir->op2 >> 8));
1123 }
1124}
1125
1126static void asm_fref(ASMState *as, IRIns *ir)
1127{
1128 Reg dest = ra_dest(as, ir, RSET_GPR);
1129 asm_fusefref(as, ir, RSET_GPR);
1130 emit_mrm(as, XO_LEA, dest, RID_MRM);
1131}
1132
1133static void asm_strref(ASMState *as, IRIns *ir)
1134{
1135 Reg dest = ra_dest(as, ir, RSET_GPR);
1136 asm_fusestrref(as, ir, RSET_GPR);
1137 if (as->mrm.base == RID_NONE)
1138 emit_loadi(as, dest, as->mrm.ofs);
1139 else if (as->mrm.base == dest && as->mrm.idx == RID_NONE)
1140 emit_gri(as, XG_ARITHi(XOg_ADD), dest, as->mrm.ofs);
1141 else
1142 emit_mrm(as, XO_LEA, dest, RID_MRM);
1143}
1144
1145/* -- Loads and stores ---------------------------------------------------- */
1146
1147static void asm_fxload(ASMState *as, IRIns *ir)
1148{
1149 Reg dest = ra_dest(as, ir, irt_isnum(ir->t) ? RSET_FPR : RSET_GPR);
1150 x86Op xo;
1151 if (ir->o == IR_FLOAD)
1152 asm_fusefref(as, ir, RSET_GPR);
1153 else
1154 asm_fusexref(as, ir->op1, RSET_GPR);
1155 /* ir->op2 is ignored -- unaligned loads are ok on x86. */
1156 switch (irt_type(ir->t)) {
1157 case IRT_I8: xo = XO_MOVSXb; break;
1158 case IRT_U8: xo = XO_MOVZXb; break;
1159 case IRT_I16: xo = XO_MOVSXw; break;
1160 case IRT_U16: xo = XO_MOVZXw; break;
1161 case IRT_NUM: xo = XMM_MOVRM(as); break;
1162 case IRT_FLOAT: xo = XO_MOVSS; break;
1163 default:
1164 if (LJ_64 && irt_is64(ir->t))
1165 dest |= REX_64;
1166 else
1167 lua_assert(irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t));
1168 xo = XO_MOV;
1169 break;
1170 }
1171 emit_mrm(as, xo, dest, RID_MRM);
1172}
1173
1174static void asm_fxstore(ASMState *as, IRIns *ir)
1175{
1176 RegSet allow = RSET_GPR;
1177 Reg src = RID_NONE, osrc = RID_NONE;
1178 int32_t k = 0;
1179 /* The IRT_I16/IRT_U16 stores should never be simplified for constant
1180 ** values since mov word [mem], imm16 has a length-changing prefix.
1181 */
1182 if (irt_isi16(ir->t) || irt_isu16(ir->t) || irt_isfp(ir->t) ||
1183 !asm_isk32(as, ir->op2, &k)) {
1184 RegSet allow8 = irt_isfp(ir->t) ? RSET_FPR :
1185 (irt_isi8(ir->t) || irt_isu8(ir->t)) ? RSET_GPR8 : RSET_GPR;
1186 src = osrc = ra_alloc1(as, ir->op2, allow8);
1187 if (!LJ_64 && !rset_test(allow8, src)) { /* Already in wrong register. */
1188 rset_clear(allow, osrc);
1189 src = ra_scratch(as, allow8);
1190 }
1191 rset_clear(allow, src);
1192 }
1193 if (ir->o == IR_FSTORE)
1194 asm_fusefref(as, IR(ir->op1), allow);
1195 else
1196 asm_fusexref(as, ir->op1, allow);
1197 /* ir->op2 is ignored -- unaligned stores are ok on x86. */
1198 if (ra_hasreg(src)) {
1199 x86Op xo;
1200 switch (irt_type(ir->t)) {
1201 case IRT_I8: case IRT_U8: xo = XO_MOVtob; src |= FORCE_REX; break;
1202 case IRT_I16: case IRT_U16: xo = XO_MOVtow; break;
1203 case IRT_NUM: xo = XO_MOVSDto; break;
1204 case IRT_FLOAT: xo = XO_MOVSSto; break;
1205#if LJ_64
1206 case IRT_LIGHTUD: lua_assert(0); /* NYI: mask 64 bit lightuserdata. */
1207#endif
1208 default:
1209 if (LJ_64 && irt_is64(ir->t))
1210 src |= REX_64;
1211 else
1212 lua_assert(irt_isint(ir->t) || irt_isu32(ir->t) || irt_isaddr(ir->t));
1213 xo = XO_MOVto;
1214 break;
1215 }
1216 emit_mrm(as, xo, src, RID_MRM);
1217 if (!LJ_64 && src != osrc) {
1218 ra_noweak(as, osrc);
1219 emit_rr(as, XO_MOV, src, osrc);
1220 }
1221 } else {
1222 if (irt_isi8(ir->t) || irt_isu8(ir->t)) {
1223 emit_i8(as, k);
1224 emit_mrm(as, XO_MOVmib, 0, RID_MRM);
1225 } else {
1226 lua_assert(irt_is64(ir->t) || irt_isint(ir->t) || irt_isu32(ir->t) ||
1227 irt_isaddr(ir->t));
1228 emit_i32(as, k);
1229 emit_mrm(as, XO_MOVmi, REX_64IR(ir, 0), RID_MRM);
1230 }
1231 }
1232}
1233
1234#if LJ_64
1235static Reg asm_load_lightud64(ASMState *as, IRIns *ir, int typecheck)
1236{
1237 if (ra_used(ir) || typecheck) {
1238 Reg dest = ra_dest(as, ir, RSET_GPR);
1239 if (typecheck) {
1240 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, dest));
1241 asm_guardcc(as, CC_NE);
1242 emit_i8(as, -2);
1243 emit_rr(as, XO_ARITHi8, XOg_CMP, tmp);
1244 emit_shifti(as, XOg_SAR|REX_64, tmp, 47);
1245 emit_rr(as, XO_MOV, tmp|REX_64, dest);
1246 }
1247 return dest;
1248 } else {
1249 return RID_NONE;
1250 }
1251}
1252#endif
1253
1254static void asm_ahuvload(ASMState *as, IRIns *ir)
1255{
1256 lua_assert(irt_isnum(ir->t) || irt_ispri(ir->t) || irt_isaddr(ir->t) ||
1257 (LJ_DUALNUM && irt_isint(ir->t)));
1258#if LJ_64
1259 if (irt_islightud(ir->t)) {
1260 Reg dest = asm_load_lightud64(as, ir, 1);
1261 if (ra_hasreg(dest)) {
1262 asm_fuseahuref(as, ir->op1, RSET_GPR);
1263 emit_mrm(as, XO_MOV, dest|REX_64, RID_MRM);
1264 }
1265 return;
1266 } else
1267#endif
1268 if (ra_used(ir)) {
1269 RegSet allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR;
1270 Reg dest = ra_dest(as, ir, allow);
1271 asm_fuseahuref(as, ir->op1, RSET_GPR);
1272 emit_mrm(as, dest < RID_MAX_GPR ? XO_MOV : XMM_MOVRM(as), dest, RID_MRM);
1273 } else {
1274 asm_fuseahuref(as, ir->op1, RSET_GPR);
1275 }
1276 /* Always do the type check, even if the load result is unused. */
1277 as->mrm.ofs += 4;
1278 asm_guardcc(as, irt_isnum(ir->t) ? CC_AE : CC_NE);
1279 if (LJ_64 && irt_type(ir->t) >= IRT_NUM) {
1280 lua_assert(irt_isinteger(ir->t) || irt_isnum(ir->t));
1281 emit_u32(as, LJ_TISNUM);
1282 emit_mrm(as, XO_ARITHi, XOg_CMP, RID_MRM);
1283 } else {
1284 emit_i8(as, irt_toitype(ir->t));
1285 emit_mrm(as, XO_ARITHi8, XOg_CMP, RID_MRM);
1286 }
1287}
1288
1289static void asm_ahustore(ASMState *as, IRIns *ir)
1290{
1291 if (irt_isnum(ir->t)) {
1292 Reg src = ra_alloc1(as, ir->op2, RSET_FPR);
1293 asm_fuseahuref(as, ir->op1, RSET_GPR);
1294 emit_mrm(as, XO_MOVSDto, src, RID_MRM);
1295#if LJ_64
1296 } else if (irt_islightud(ir->t)) {
1297 Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
1298 asm_fuseahuref(as, ir->op1, rset_exclude(RSET_GPR, src));
1299 emit_mrm(as, XO_MOVto, src|REX_64, RID_MRM);
1300#endif
1301 } else {
1302 IRIns *irr = IR(ir->op2);
1303 RegSet allow = RSET_GPR;
1304 Reg src = RID_NONE;
1305 if (!irref_isk(ir->op2)) {
1306 src = ra_alloc1(as, ir->op2, allow);
1307 rset_clear(allow, src);
1308 }
1309 asm_fuseahuref(as, ir->op1, allow);
1310 if (ra_hasreg(src)) {
1311 emit_mrm(as, XO_MOVto, src, RID_MRM);
1312 } else if (!irt_ispri(irr->t)) {
1313 lua_assert(irt_isaddr(ir->t) || (LJ_DUALNUM && irt_isinteger(ir->t)));
1314 emit_i32(as, irr->i);
1315 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
1316 }
1317 as->mrm.ofs += 4;
1318 emit_i32(as, (int32_t)irt_toitype(ir->t));
1319 emit_mrm(as, XO_MOVmi, 0, RID_MRM);
1320 }
1321}
1322
1323static void asm_sload(ASMState *as, IRIns *ir)
1324{
1325 int32_t ofs = 8*((int32_t)ir->op1-1) + ((ir->op2 & IRSLOAD_FRAME) ? 4 : 0);
1326 IRType1 t = ir->t;
1327 Reg base;
1328 lua_assert(!(ir->op2 & IRSLOAD_PARENT)); /* Handled by asm_head_side(). */
1329 lua_assert(irt_isguard(t) || !(ir->op2 & IRSLOAD_TYPECHECK));
1330 lua_assert(LJ_DUALNUM ||
1331 !irt_isint(t) || (ir->op2 & (IRSLOAD_CONVERT|IRSLOAD_FRAME)));
1332 if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
1333 Reg left = ra_scratch(as, RSET_FPR);
1334 asm_tointg(as, ir, left); /* Frees dest reg. Do this before base alloc. */
1335 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1336 emit_rmro(as, XMM_MOVRM(as), left, base, ofs);
1337 t.irt = IRT_NUM; /* Continue with a regular number type check. */
1338#if LJ_64
1339 } else if (irt_islightud(t)) {
1340 Reg dest = asm_load_lightud64(as, ir, (ir->op2 & IRSLOAD_TYPECHECK));
1341 if (ra_hasreg(dest)) {
1342 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1343 emit_rmro(as, XO_MOV, dest|REX_64, base, ofs);
1344 }
1345 return;
1346#endif
1347 } else if (ra_used(ir)) {
1348 RegSet allow = irt_isnum(t) ? RSET_FPR : RSET_GPR;
1349 Reg dest = ra_dest(as, ir, allow);
1350 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1351 lua_assert(irt_isnum(t) || irt_isint(t) || irt_isaddr(t));
1352 if ((ir->op2 & IRSLOAD_CONVERT)) {
1353 t.irt = irt_isint(t) ? IRT_NUM : IRT_INT; /* Check for original type. */
1354 emit_rmro(as, irt_isint(t) ? XO_CVTSI2SD : XO_CVTSD2SI, dest, base, ofs);
1355 } else if (irt_isnum(t)) {
1356 emit_rmro(as, XMM_MOVRM(as), dest, base, ofs);
1357 } else {
1358 emit_rmro(as, XO_MOV, dest, base, ofs);
1359 }
1360 } else {
1361 if (!(ir->op2 & IRSLOAD_TYPECHECK))
1362 return; /* No type check: avoid base alloc. */
1363 base = ra_alloc1(as, REF_BASE, RSET_GPR);
1364 }
1365 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1366 /* Need type check, even if the load result is unused. */
1367 asm_guardcc(as, irt_isnum(t) ? CC_AE : CC_NE);
1368 if (LJ_64 && irt_type(t) >= IRT_NUM) {
1369 lua_assert(irt_isinteger(t) || irt_isnum(t));
1370 emit_u32(as, LJ_TISNUM);
1371 emit_rmro(as, XO_ARITHi, XOg_CMP, base, ofs+4);
1372 } else {
1373 emit_i8(as, irt_toitype(t));
1374 emit_rmro(as, XO_ARITHi8, XOg_CMP, base, ofs+4);
1375 }
1376 }
1377}
1378
1379/* -- Allocations --------------------------------------------------------- */
1380
1381#if LJ_HASFFI
1382static void asm_cnew(ASMState *as, IRIns *ir)
1383{
1384 CTState *cts = ctype_ctsG(J2G(as->J));
1385 CTypeID typeid = (CTypeID)IR(ir->op1)->i;
1386 CTSize sz = (ir->o == IR_CNEWI || ir->op2 == REF_NIL) ?
1387 lj_ctype_size(cts, typeid) : (CTSize)IR(ir->op2)->i;
1388 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1389 IRRef args[2];
1390 lua_assert(sz != CTSIZE_INVALID);
1391
1392 args[0] = ASMREF_L; /* lua_State *L */
1393 args[1] = ASMREF_TMP1; /* MSize size */
1394 as->gcsteps++;
1395 asm_setupresult(as, ir, ci); /* GCcdata * */
1396
1397 /* Initialize immutable cdata object. */
1398 if (ir->o == IR_CNEWI) {
1399 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1400#if LJ_64
1401 Reg r64 = sz == 8 ? REX_64 : 0;
1402 if (irref_isk(ir->op2)) {
1403 IRIns *irk = IR(ir->op2);
1404 uint64_t k = irk->o == IR_KINT64 ? ir_k64(irk)->u64 :
1405 (uint64_t)(uint32_t)irk->i;
1406 if (sz == 4 || checki32((int64_t)k)) {
1407 emit_i32(as, (int32_t)k);
1408 emit_rmro(as, XO_MOVmi, r64, RID_RET, sizeof(GCcdata));
1409 } else {
1410 emit_movtomro(as, RID_ECX + r64, RID_RET, sizeof(GCcdata));
1411 emit_loadu64(as, RID_ECX, k);
1412 }
1413 } else {
1414 Reg r = ra_alloc1(as, ir->op2, allow);
1415 emit_movtomro(as, r + r64, RID_RET, sizeof(GCcdata));
1416 }
1417#else
1418 int32_t ofs = sizeof(GCcdata);
1419 if (LJ_HASFFI && sz == 8) {
1420 ofs += 4; ir++;
1421 lua_assert(ir->o == IR_HIOP);
1422 }
1423 do {
1424 if (irref_isk(ir->op2)) {
1425 emit_movmroi(as, RID_RET, ofs, IR(ir->op2)->i);
1426 } else {
1427 Reg r = ra_alloc1(as, ir->op2, allow);
1428 emit_movtomro(as, r, RID_RET, ofs);
1429 rset_clear(allow, r);
1430 }
1431 if (!LJ_HASFFI || ofs == sizeof(GCcdata)) break;
1432 ofs -= 4; ir--;
1433 } while (1);
1434#endif
1435 lua_assert(sz == 4 || (sz == 8 && (LJ_64 || LJ_HASFFI)));
1436 }
1437
1438 /* Combine initialization of marked, gct and typeid. */
1439 emit_movtomro(as, RID_ECX, RID_RET, offsetof(GCcdata, marked));
1440 emit_gri(as, XG_ARITHi(XOg_OR), RID_ECX,
1441 (int32_t)((~LJ_TCDATA<<8)+(typeid<<16)));
1442 emit_gri(as, XG_ARITHi(XOg_AND), RID_ECX, LJ_GC_WHITES);
1443 emit_opgl(as, XO_MOVZXb, RID_ECX, gc.currentwhite);
1444
1445 asm_gencall(as, ci, args);
1446 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)(sz+sizeof(GCcdata)));
1447}
1448#else
1449#define asm_cnew(as, ir) ((void)0)
1450#endif
1451
1452/* -- Write barriers ------------------------------------------------------ */
1453
1454static void asm_tbar(ASMState *as, IRIns *ir)
1455{
1456 Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1457 Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1458 MCLabel l_end = emit_label(as);
1459 emit_movtomro(as, tmp, tab, offsetof(GCtab, gclist));
1460 emit_setgl(as, tab, gc.grayagain);
1461 emit_getgl(as, tmp, gc.grayagain);
1462 emit_i8(as, ~LJ_GC_BLACK);
1463 emit_rmro(as, XO_ARITHib, XOg_AND, tab, offsetof(GCtab, marked));
1464 emit_sjcc(as, CC_Z, l_end);
1465 emit_i8(as, LJ_GC_BLACK);
1466 emit_rmro(as, XO_GROUP3b, XOg_TEST, tab, offsetof(GCtab, marked));
1467}
1468
1469static void asm_obar(ASMState *as, IRIns *ir)
1470{
1471 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1472 IRRef args[2];
1473 MCLabel l_end;
1474 Reg obj;
1475 /* No need for other object barriers (yet). */
1476 lua_assert(IR(ir->op1)->o == IR_UREFC);
1477 ra_evictset(as, RSET_SCRATCH);
1478 l_end = emit_label(as);
1479 args[0] = ASMREF_TMP1; /* global_State *g */
1480 args[1] = ir->op1; /* TValue *tv */
1481 asm_gencall(as, ci, args);
1482 emit_loada(as, ra_releasetmp(as, ASMREF_TMP1), J2G(as->J));
1483 obj = IR(ir->op1)->r;
1484 emit_sjcc(as, CC_Z, l_end);
1485 emit_i8(as, LJ_GC_WHITES);
1486 if (irref_isk(ir->op2)) {
1487 GCobj *vp = ir_kgc(IR(ir->op2));
1488 emit_rma(as, XO_GROUP3b, XOg_TEST, &vp->gch.marked);
1489 } else {
1490 Reg val = ra_alloc1(as, ir->op2, rset_exclude(RSET_SCRATCH&RSET_GPR, obj));
1491 emit_rmro(as, XO_GROUP3b, XOg_TEST, val, (int32_t)offsetof(GChead, marked));
1492 }
1493 emit_sjcc(as, CC_Z, l_end);
1494 emit_i8(as, LJ_GC_BLACK);
1495 emit_rmro(as, XO_GROUP3b, XOg_TEST, obj,
1496 (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1497}
1498
1499/* -- FP/int arithmetic and logic operations ------------------------------ */
1500
1501/* Load reference onto x87 stack. Force a spill to memory if needed. */
1502static void asm_x87load(ASMState *as, IRRef ref)
1503{
1504 IRIns *ir = IR(ref);
1505 if (ir->o == IR_KNUM) {
1506 cTValue *tv = ir_knum(ir);
1507 if (tvispzero(tv)) /* Use fldz only for +0. */
1508 emit_x87op(as, XI_FLDZ);
1509 else if (tvispone(tv))
1510 emit_x87op(as, XI_FLD1);
1511 else
1512 emit_rma(as, XO_FLDq, XOg_FLDq, tv);
1513 } else if (ir->o == IR_CONV && ir->op2 == IRCONV_NUM_INT && !ra_used(ir) &&
1514 !irref_isk(ir->op1) && mayfuse(as, ir->op1)) {
1515 IRIns *iri = IR(ir->op1);
1516 emit_rmro(as, XO_FILDd, XOg_FILDd, RID_ESP, ra_spill(as, iri));
1517 } else {
1518 emit_mrm(as, XO_FLDq, XOg_FLDq, asm_fuseload(as, ref, RSET_EMPTY));
1519 }
1520}
1521
1522/* Try to rejoin pow from EXP2, MUL and LOG2 (if still unsplit). */
1523static int fpmjoin_pow(ASMState *as, IRIns *ir)
1524{
1525 IRIns *irp = IR(ir->op1);
1526 if (irp == ir-1 && irp->o == IR_MUL && !ra_used(irp)) {
1527 IRIns *irpp = IR(irp->op1);
1528 if (irpp == ir-2 && irpp->o == IR_FPMATH &&
1529 irpp->op2 == IRFPM_LOG2 && !ra_used(irpp)) {
1530 /* The modified regs must match with the *.dasc implementation. */
1531 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM2+1)|RID2RSET(RID_EAX);
1532 IRIns *irx;
1533 if (ra_hasreg(ir->r))
1534 rset_clear(drop, ir->r); /* Dest reg handled below. */
1535 ra_evictset(as, drop);
1536 ra_destreg(as, ir, RID_XMM0);
1537 emit_call(as, lj_vm_pow_sse);
1538 irx = IR(irpp->op1);
1539 if (ra_noreg(irx->r) && ra_gethint(irx->r) == RID_XMM1)
1540 irx->r = RID_INIT; /* Avoid allocating xmm1 for x. */
1541 ra_left(as, RID_XMM0, irpp->op1);
1542 ra_left(as, RID_XMM1, irp->op2);
1543 return 1;
1544 }
1545 }
1546 return 0;
1547}
1548
1549static void asm_fpmath(ASMState *as, IRIns *ir)
1550{
1551 IRFPMathOp fpm = ir->o == IR_FPMATH ? (IRFPMathOp)ir->op2 : IRFPM_OTHER;
1552 if (fpm == IRFPM_SQRT) {
1553 Reg dest = ra_dest(as, ir, RSET_FPR);
1554 Reg left = asm_fuseload(as, ir->op1, RSET_FPR);
1555 emit_mrm(as, XO_SQRTSD, dest, left);
1556 } else if (fpm <= IRFPM_TRUNC) {
1557 if (as->flags & JIT_F_SSE4_1) { /* SSE4.1 has a rounding instruction. */
1558 Reg dest = ra_dest(as, ir, RSET_FPR);
1559 Reg left = asm_fuseload(as, ir->op1, RSET_FPR);
1560 /* ROUNDSD has a 4-byte opcode which doesn't fit in x86Op.
1561 ** Let's pretend it's a 3-byte opcode, and compensate afterwards.
1562 ** This is atrocious, but the alternatives are much worse.
1563 */
1564 /* Round down/up/trunc == 1001/1010/1011. */
1565 emit_i8(as, 0x09 + fpm);
1566 emit_mrm(as, XO_ROUNDSD, dest, left);
1567 if (LJ_64 && as->mcp[1] != (MCode)(XO_ROUNDSD >> 16)) {
1568 as->mcp[0] = as->mcp[1]; as->mcp[1] = 0x0f; /* Swap 0F and REX. */
1569 }
1570 *--as->mcp = 0x66; /* 1st byte of ROUNDSD opcode. */
1571 } else { /* Call helper functions for SSE2 variant. */
1572 /* The modified regs must match with the *.dasc implementation. */
1573 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM3+1)|RID2RSET(RID_EAX);
1574 if (ra_hasreg(ir->r))
1575 rset_clear(drop, ir->r); /* Dest reg handled below. */
1576 ra_evictset(as, drop);
1577 ra_destreg(as, ir, RID_XMM0);
1578 emit_call(as, fpm == IRFPM_FLOOR ? lj_vm_floor_sse :
1579 fpm == IRFPM_CEIL ? lj_vm_ceil_sse : lj_vm_trunc_sse);
1580 ra_left(as, RID_XMM0, ir->op1);
1581 }
1582 } else if (fpm == IRFPM_EXP2 && fpmjoin_pow(as, ir)) {
1583 /* Rejoined to pow(). */
1584 } else { /* Handle x87 ops. */
1585 int32_t ofs = sps_scale(ir->s); /* Use spill slot or temp slots. */
1586 Reg dest = ir->r;
1587 if (ra_hasreg(dest)) {
1588 ra_free(as, dest);
1589 ra_modified(as, dest);
1590 emit_rmro(as, XMM_MOVRM(as), dest, RID_ESP, ofs);
1591 }
1592 emit_rmro(as, XO_FSTPq, XOg_FSTPq, RID_ESP, ofs);
1593 switch (fpm) { /* st0 = lj_vm_*(st0) */
1594 case IRFPM_EXP: emit_call(as, lj_vm_exp); break;
1595 case IRFPM_EXP2: emit_call(as, lj_vm_exp2); break;
1596 case IRFPM_SIN: emit_x87op(as, XI_FSIN); break;
1597 case IRFPM_COS: emit_x87op(as, XI_FCOS); break;
1598 case IRFPM_TAN: emit_x87op(as, XI_FPOP); emit_x87op(as, XI_FPTAN); break;
1599 case IRFPM_LOG: case IRFPM_LOG2: case IRFPM_LOG10:
1600 /* Note: the use of fyl2xp1 would be pointless here. When computing
1601 ** log(1.0+eps) the precision is already lost after 1.0 is added.
1602 ** Subtracting 1.0 won't recover it. OTOH math.log1p would make sense.
1603 */
1604 emit_x87op(as, XI_FYL2X); break;
1605 case IRFPM_OTHER:
1606 switch (ir->o) {
1607 case IR_ATAN2:
1608 emit_x87op(as, XI_FPATAN); asm_x87load(as, ir->op2); break;
1609 case IR_LDEXP:
1610 emit_x87op(as, XI_FPOP1); emit_x87op(as, XI_FSCALE); break;
1611 default: lua_assert(0); break;
1612 }
1613 break;
1614 default: lua_assert(0); break;
1615 }
1616 asm_x87load(as, ir->op1);
1617 switch (fpm) {
1618 case IRFPM_LOG: emit_x87op(as, XI_FLDLN2); break;
1619 case IRFPM_LOG2: emit_x87op(as, XI_FLD1); break;
1620 case IRFPM_LOG10: emit_x87op(as, XI_FLDLG2); break;
1621 case IRFPM_OTHER:
1622 if (ir->o == IR_LDEXP) asm_x87load(as, ir->op2);
1623 break;
1624 default: break;
1625 }
1626 }
1627}
1628
1629static void asm_fppowi(ASMState *as, IRIns *ir)
1630{
1631 /* The modified regs must match with the *.dasc implementation. */
1632 RegSet drop = RSET_RANGE(RID_XMM0, RID_XMM1+1)|RID2RSET(RID_EAX);
1633 if (ra_hasreg(ir->r))
1634 rset_clear(drop, ir->r); /* Dest reg handled below. */
1635 ra_evictset(as, drop);
1636 ra_destreg(as, ir, RID_XMM0);
1637 emit_call(as, lj_vm_powi_sse);
1638 ra_left(as, RID_XMM0, ir->op1);
1639 ra_left(as, RID_EAX, ir->op2);
1640}
1641
1642#if LJ_64 && LJ_HASFFI
1643static void asm_arith64(ASMState *as, IRIns *ir, IRCallID id)
1644{
1645 const CCallInfo *ci = &lj_ir_callinfo[id];
1646 IRRef args[2];
1647 args[0] = ir->op1;
1648 args[1] = ir->op2;
1649 asm_setupresult(as, ir, ci);
1650 asm_gencall(as, ci, args);
1651}
1652#endif
1653
1654static int asm_swapops(ASMState *as, IRIns *ir)
1655{
1656 IRIns *irl = IR(ir->op1);
1657 IRIns *irr = IR(ir->op2);
1658 lua_assert(ra_noreg(irr->r));
1659 if (!irm_iscomm(lj_ir_mode[ir->o]))
1660 return 0; /* Can't swap non-commutative operations. */
1661 if (irref_isk(ir->op2))
1662 return 0; /* Don't swap constants to the left. */
1663 if (ra_hasreg(irl->r))
1664 return 1; /* Swap if left already has a register. */
1665 if (ra_samehint(ir->r, irr->r))
1666 return 1; /* Swap if dest and right have matching hints. */
1667 if (as->curins > as->loopref) { /* In variant part? */
1668 if (ir->op2 < as->loopref && !irt_isphi(irr->t))
1669 return 0; /* Keep invariants on the right. */
1670 if (ir->op1 < as->loopref && !irt_isphi(irl->t))
1671 return 1; /* Swap invariants to the right. */
1672 }
1673 if (opisfusableload(irl->o))
1674 return 1; /* Swap fusable loads to the right. */
1675 return 0; /* Otherwise don't swap. */
1676}
1677
1678static void asm_fparith(ASMState *as, IRIns *ir, x86Op xo)
1679{
1680 IRRef lref = ir->op1;
1681 IRRef rref = ir->op2;
1682 RegSet allow = RSET_FPR;
1683 Reg dest;
1684 Reg right = IR(rref)->r;
1685 if (ra_hasreg(right)) {
1686 rset_clear(allow, right);
1687 ra_noweak(as, right);
1688 }
1689 dest = ra_dest(as, ir, allow);
1690 if (lref == rref) {
1691 right = dest;
1692 } else if (ra_noreg(right)) {
1693 if (asm_swapops(as, ir)) {
1694 IRRef tmp = lref; lref = rref; rref = tmp;
1695 }
1696 right = asm_fuseload(as, rref, rset_clear(allow, dest));
1697 }
1698 emit_mrm(as, xo, dest, right);
1699 ra_left(as, dest, lref);
1700}
1701
1702static void asm_intarith(ASMState *as, IRIns *ir, x86Arith xa)
1703{
1704 IRRef lref = ir->op1;
1705 IRRef rref = ir->op2;
1706 RegSet allow = RSET_GPR;
1707 Reg dest, right;
1708 int32_t k = 0;
1709 if (as->flagmcp == as->mcp) { /* Drop test r,r instruction. */
1710 as->flagmcp = NULL;
1711 as->mcp += (LJ_64 && *as->mcp != XI_TEST) ? 3 : 2;
1712 }
1713 right = IR(rref)->r;
1714 if (ra_hasreg(right)) {
1715 rset_clear(allow, right);
1716 ra_noweak(as, right);
1717 }
1718 dest = ra_dest(as, ir, allow);
1719 if (lref == rref) {
1720 right = dest;
1721 } else if (ra_noreg(right) && !asm_isk32(as, rref, &k)) {
1722 if (asm_swapops(as, ir)) {
1723 IRRef tmp = lref; lref = rref; rref = tmp;
1724 }
1725 right = asm_fuseload(as, rref, rset_clear(allow, dest));
1726 }
1727 if (irt_isguard(ir->t)) /* For IR_ADDOV etc. */
1728 asm_guardcc(as, CC_O);
1729 if (xa != XOg_X_IMUL) {
1730 if (ra_hasreg(right))
1731 emit_mrm(as, XO_ARITH(xa), REX_64IR(ir, dest), right);
1732 else
1733 emit_gri(as, XG_ARITHi(xa), REX_64IR(ir, dest), k);
1734 } else if (ra_hasreg(right)) { /* IMUL r, mrm. */
1735 emit_mrm(as, XO_IMUL, REX_64IR(ir, dest), right);
1736 } else { /* IMUL r, r, k. */
1737 /* NYI: use lea/shl/add/sub (FOLD only does 2^k) depending on CPU. */
1738 Reg left = asm_fuseload(as, lref, RSET_GPR);
1739 x86Op xo;
1740 if (checki8(k)) { emit_i8(as, k); xo = XO_IMULi8;
1741 } else { emit_i32(as, k); xo = XO_IMULi; }
1742 emit_mrm(as, xo, REX_64IR(ir, dest), left);
1743 return;
1744 }
1745 ra_left(as, dest, lref);
1746}
1747
1748/* LEA is really a 4-operand ADD with an independent destination register,
1749** up to two source registers and an immediate. One register can be scaled
1750** by 1, 2, 4 or 8. This can be used to avoid moves or to fuse several
1751** instructions.
1752**
1753** Currently only a few common cases are supported:
1754** - 3-operand ADD: y = a+b; y = a+k with a and b already allocated
1755** - Left ADD fusion: y = (a+b)+k; y = (a+k)+b
1756** - Right ADD fusion: y = a+(b+k)
1757** The ommited variants have already been reduced by FOLD.
1758**
1759** There are more fusion opportunities, like gathering shifts or joining
1760** common references. But these are probably not worth the trouble, since
1761** array indexing is not decomposed and already makes use of all fields
1762** of the ModRM operand.
1763*/
1764static int asm_lea(ASMState *as, IRIns *ir)
1765{
1766 IRIns *irl = IR(ir->op1);
1767 IRIns *irr = IR(ir->op2);
1768 RegSet allow = RSET_GPR;
1769 Reg dest;
1770 as->mrm.base = as->mrm.idx = RID_NONE;
1771 as->mrm.scale = XM_SCALE1;
1772 as->mrm.ofs = 0;
1773 if (ra_hasreg(irl->r)) {
1774 rset_clear(allow, irl->r);
1775 ra_noweak(as, irl->r);
1776 as->mrm.base = irl->r;
1777 if (irref_isk(ir->op2) || ra_hasreg(irr->r)) {
1778 /* The PHI renaming logic does a better job in some cases. */
1779 if (ra_hasreg(ir->r) &&
1780 ((irt_isphi(irl->t) && as->phireg[ir->r] == ir->op1) ||
1781 (irt_isphi(irr->t) && as->phireg[ir->r] == ir->op2)))
1782 return 0;
1783 if (irref_isk(ir->op2)) {
1784 as->mrm.ofs = irr->i;
1785 } else {
1786 rset_clear(allow, irr->r);
1787 ra_noweak(as, irr->r);
1788 as->mrm.idx = irr->r;
1789 }
1790 } else if (irr->o == IR_ADD && mayfuse(as, ir->op2) &&
1791 irref_isk(irr->op2)) {
1792 Reg idx = ra_alloc1(as, irr->op1, allow);
1793 rset_clear(allow, idx);
1794 as->mrm.idx = (uint8_t)idx;
1795 as->mrm.ofs = IR(irr->op2)->i;
1796 } else {
1797 return 0;
1798 }
1799 } else if (ir->op1 != ir->op2 && irl->o == IR_ADD && mayfuse(as, ir->op1) &&
1800 (irref_isk(ir->op2) || irref_isk(irl->op2))) {
1801 Reg idx, base = ra_alloc1(as, irl->op1, allow);
1802 rset_clear(allow, base);
1803 as->mrm.base = (uint8_t)base;
1804 if (irref_isk(ir->op2)) {
1805 as->mrm.ofs = irr->i;
1806 idx = ra_alloc1(as, irl->op2, allow);
1807 } else {
1808 as->mrm.ofs = IR(irl->op2)->i;
1809 idx = ra_alloc1(as, ir->op2, allow);
1810 }
1811 rset_clear(allow, idx);
1812 as->mrm.idx = (uint8_t)idx;
1813 } else {
1814 return 0;
1815 }
1816 dest = ra_dest(as, ir, allow);
1817 emit_mrm(as, XO_LEA, dest, RID_MRM);
1818 return 1; /* Success. */
1819}
1820
1821static void asm_add(ASMState *as, IRIns *ir)
1822{
1823 if (irt_isnum(ir->t))
1824 asm_fparith(as, ir, XO_ADDSD);
1825 else if ((as->flags & JIT_F_LEA_AGU) || as->flagmcp == as->mcp ||
1826 irt_is64(ir->t) || !asm_lea(as, ir))
1827 asm_intarith(as, ir, XOg_ADD);
1828}
1829
1830static void asm_neg_not(ASMState *as, IRIns *ir, x86Group3 xg)
1831{
1832 Reg dest = ra_dest(as, ir, RSET_GPR);
1833 emit_rr(as, XO_GROUP3, REX_64IR(ir, xg), dest);
1834 ra_left(as, dest, ir->op1);
1835}
1836
1837static void asm_min_max(ASMState *as, IRIns *ir, int cc)
1838{
1839 Reg right, dest = ra_dest(as, ir, RSET_GPR);
1840 IRRef lref = ir->op1, rref = ir->op2;
1841 if (irref_isk(rref)) { lref = rref; rref = ir->op1; }
1842 right = ra_alloc1(as, rref, rset_exclude(RSET_GPR, dest));
1843 emit_rr(as, XO_CMOV + (cc<<24), REX_64IR(ir, dest), right);
1844 emit_rr(as, XO_CMP, REX_64IR(ir, dest), right);
1845 ra_left(as, dest, lref);
1846}
1847
1848static void asm_bitswap(ASMState *as, IRIns *ir)
1849{
1850 Reg dest = ra_dest(as, ir, RSET_GPR);
1851 as->mcp = emit_op(XO_BSWAP + ((dest&7) << 24),
1852 REX_64IR(ir, dest), 0, 0, as->mcp, 1);
1853 ra_left(as, dest, ir->op1);
1854}
1855
1856static void asm_bitshift(ASMState *as, IRIns *ir, x86Shift xs)
1857{
1858 IRRef rref = ir->op2;
1859 IRIns *irr = IR(rref);
1860 Reg dest;
1861 if (irref_isk(rref)) { /* Constant shifts. */
1862 int shift;
1863 dest = ra_dest(as, ir, RSET_GPR);
1864 shift = irr->i & (irt_is64(ir->t) ? 63 : 31);
1865 switch (shift) {
1866 case 0: break;
1867 case 1: emit_rr(as, XO_SHIFT1, REX_64IR(ir, xs), dest); break;
1868 default: emit_shifti(as, REX_64IR(ir, xs), dest, shift); break;
1869 }
1870 } else { /* Variable shifts implicitly use register cl (i.e. ecx). */
1871 RegSet allow = rset_exclude(RSET_GPR, RID_ECX);
1872 Reg right = irr->r;
1873 if (ra_noreg(right)) {
1874 right = ra_allocref(as, rref, RID2RSET(RID_ECX));
1875 } else if (right != RID_ECX) {
1876 rset_clear(allow, right);
1877 ra_scratch(as, RID2RSET(RID_ECX));
1878 }
1879 dest = ra_dest(as, ir, allow);
1880 emit_rr(as, XO_SHIFTcl, REX_64IR(ir, xs), dest);
1881 if (right != RID_ECX) {
1882 ra_noweak(as, right);
1883 emit_rr(as, XO_MOV, RID_ECX, right);
1884 }
1885 }
1886 ra_left(as, dest, ir->op1);
1887 /*
1888 ** Note: avoid using the flags resulting from a shift or rotate!
1889 ** All of them cause a partial flag stall, except for r,1 shifts
1890 ** (but not rotates). And a shift count of 0 leaves the flags unmodified.
1891 */
1892}
1893
1894/* -- Comparisons --------------------------------------------------------- */
1895
1896/* Virtual flags for unordered FP comparisons. */
1897#define VCC_U 0x1000 /* Unordered. */
1898#define VCC_P 0x2000 /* Needs extra CC_P branch. */
1899#define VCC_S 0x4000 /* Swap avoids CC_P branch. */
1900#define VCC_PS (VCC_P|VCC_S)
1901
1902/* Map of comparisons to flags. ORDER IR. */
1903#define COMPFLAGS(ci, cin, cu, cf) ((ci)+((cu)<<4)+((cin)<<8)+(cf))
1904static const uint16_t asm_compmap[IR_ABC+1] = {
1905 /* signed non-eq unsigned flags */
1906 /* LT */ COMPFLAGS(CC_GE, CC_G, CC_AE, VCC_PS),
1907 /* GE */ COMPFLAGS(CC_L, CC_L, CC_B, 0),
1908 /* LE */ COMPFLAGS(CC_G, CC_G, CC_A, VCC_PS),
1909 /* GT */ COMPFLAGS(CC_LE, CC_L, CC_BE, 0),
1910 /* ULT */ COMPFLAGS(CC_AE, CC_A, CC_AE, VCC_U),
1911 /* UGE */ COMPFLAGS(CC_B, CC_B, CC_B, VCC_U|VCC_PS),
1912 /* ULE */ COMPFLAGS(CC_A, CC_A, CC_A, VCC_U),
1913 /* UGT */ COMPFLAGS(CC_BE, CC_B, CC_BE, VCC_U|VCC_PS),
1914 /* EQ */ COMPFLAGS(CC_NE, CC_NE, CC_NE, VCC_P),
1915 /* NE */ COMPFLAGS(CC_E, CC_E, CC_E, VCC_U|VCC_P),
1916 /* ABC */ COMPFLAGS(CC_BE, CC_B, CC_BE, VCC_U|VCC_PS) /* Same as UGT. */
1917};
1918
1919/* FP and integer comparisons. */
1920static void asm_comp(ASMState *as, IRIns *ir, uint32_t cc)
1921{
1922 if (irt_isnum(ir->t)) {
1923 IRRef lref = ir->op1;
1924 IRRef rref = ir->op2;
1925 Reg left, right;
1926 MCLabel l_around;
1927 /*
1928 ** An extra CC_P branch is required to preserve ordered/unordered
1929 ** semantics for FP comparisons. This can be avoided by swapping
1930 ** the operands and inverting the condition (except for EQ and UNE).
1931 ** So always try to swap if possible.
1932 **
1933 ** Another option would be to swap operands to achieve better memory
1934 ** operand fusion. But it's unlikely that this outweighs the cost
1935 ** of the extra branches.
1936 */
1937 if (cc & VCC_S) { /* Swap? */
1938 IRRef tmp = lref; lref = rref; rref = tmp;
1939 cc ^= (VCC_PS|(5<<4)); /* A <-> B, AE <-> BE, PS <-> none */
1940 }
1941 left = ra_alloc1(as, lref, RSET_FPR);
1942 right = asm_fuseload(as, rref, rset_exclude(RSET_FPR, left));
1943 l_around = emit_label(as);
1944 asm_guardcc(as, cc >> 4);
1945 if (cc & VCC_P) { /* Extra CC_P branch required? */
1946 if (!(cc & VCC_U)) {
1947 asm_guardcc(as, CC_P); /* Branch to exit for ordered comparisons. */
1948 } else if (l_around != as->invmcp) {
1949 emit_sjcc(as, CC_P, l_around); /* Branch around for unordered. */
1950 } else {
1951 /* Patched to mcloop by asm_loop_fixup. */
1952 as->loopinv = 2;
1953 if (as->realign)
1954 emit_sjcc(as, CC_P, as->mcp);
1955 else
1956 emit_jcc(as, CC_P, as->mcp);
1957 }
1958 }
1959 emit_mrm(as, XO_UCOMISD, left, right);
1960 } else {
1961 IRRef lref = ir->op1, rref = ir->op2;
1962 IROp leftop = (IROp)(IR(lref)->o);
1963 Reg r64 = REX_64IR(ir, 0);
1964 int32_t imm = 0;
1965 lua_assert(irt_is64(ir->t) || irt_isint(ir->t) || irt_isaddr(ir->t));
1966 /* Swap constants (only for ABC) and fusable loads to the right. */
1967 if (irref_isk(lref) || (!irref_isk(rref) && opisfusableload(leftop))) {
1968 if ((cc & 0xc) == 0xc) cc ^= 3; /* L <-> G, LE <-> GE */
1969 else if ((cc & 0xa) == 0x2) cc ^= 5; /* A <-> B, AE <-> BE */
1970 lref = ir->op2; rref = ir->op1;
1971 }
1972 if (asm_isk32(as, rref, &imm)) {
1973 IRIns *irl = IR(lref);
1974 /* Check wether we can use test ins. Not for unsigned, since CF=0. */
1975 int usetest = (imm == 0 && (cc & 0xa) != 0x2);
1976 if (usetest && irl->o == IR_BAND && irl+1 == ir && !ra_used(irl)) {
1977 /* Combine comp(BAND(ref, r/imm), 0) into test mrm, r/imm. */
1978 Reg right, left = RID_NONE;
1979 RegSet allow = RSET_GPR;
1980 if (!asm_isk32(as, irl->op2, &imm)) {
1981 left = ra_alloc1(as, irl->op2, allow);
1982 rset_clear(allow, left);
1983 } else { /* Try to Fuse IRT_I8/IRT_U8 loads, too. See below. */
1984 IRIns *irll = IR(irl->op1);
1985 if (opisfusableload((IROp)irll->o) &&
1986 (irt_isi8(irll->t) || irt_isu8(irll->t))) {
1987 IRType1 origt = irll->t; /* Temporarily flip types. */
1988 irll->t.irt = (irll->t.irt & ~IRT_TYPE) | IRT_INT;
1989 as->curins--; /* Skip to BAND to avoid failing in noconflict(). */
1990 right = asm_fuseload(as, irl->op1, RSET_GPR);
1991 as->curins++;
1992 irll->t = origt;
1993 if (right != RID_MRM) goto test_nofuse;
1994 /* Fusion succeeded, emit test byte mrm, imm8. */
1995 asm_guardcc(as, cc);
1996 emit_i8(as, (imm & 0xff));
1997 emit_mrm(as, XO_GROUP3b, XOg_TEST, RID_MRM);
1998 return;
1999 }
2000 }
2001 as->curins--; /* Skip to BAND to avoid failing in noconflict(). */
2002 right = asm_fuseload(as, irl->op1, allow);
2003 as->curins++; /* Undo the above. */
2004 test_nofuse:
2005 asm_guardcc(as, cc);
2006 if (ra_noreg(left)) {
2007 emit_i32(as, imm);
2008 emit_mrm(as, XO_GROUP3, r64 + XOg_TEST, right);
2009 } else {
2010 emit_mrm(as, XO_TEST, r64 + left, right);
2011 }
2012 } else {
2013 Reg left;
2014 if (opisfusableload((IROp)irl->o) &&
2015 ((irt_isu8(irl->t) && checku8(imm)) ||
2016 ((irt_isi8(irl->t) || irt_isi16(irl->t)) && checki8(imm)) ||
2017 (irt_isu16(irl->t) && checku16(imm) && checki8((int16_t)imm)))) {
2018 /* Only the IRT_INT case is fused by asm_fuseload.
2019 ** The IRT_I8/IRT_U8 loads and some IRT_I16/IRT_U16 loads
2020 ** are handled here.
2021 ** Note that cmp word [mem], imm16 should not be generated,
2022 ** since it has a length-changing prefix. Compares of a word
2023 ** against a sign-extended imm8 are ok, however.
2024 */
2025 IRType1 origt = irl->t; /* Temporarily flip types. */
2026 irl->t.irt = (irl->t.irt & ~IRT_TYPE) | IRT_INT;
2027 left = asm_fuseload(as, lref, RSET_GPR);
2028 irl->t = origt;
2029 if (left == RID_MRM) { /* Fusion succeeded? */
2030 asm_guardcc(as, cc);
2031 emit_i8(as, imm);
2032 emit_mrm(as, (irt_isi8(origt) || irt_isu8(origt)) ?
2033 XO_ARITHib : XO_ARITHiw8, r64 + XOg_CMP, RID_MRM);
2034 return;
2035 } /* Otherwise handle register case as usual. */
2036 } else {
2037 left = asm_fuseload(as, lref, RSET_GPR);
2038 }
2039 asm_guardcc(as, cc);
2040 if (usetest && left != RID_MRM) {
2041 /* Use test r,r instead of cmp r,0. */
2042 emit_rr(as, XO_TEST, r64 + left, left);
2043 if (irl+1 == ir) /* Referencing previous ins? */
2044 as->flagmcp = as->mcp; /* Set flag to drop test r,r if possible. */
2045 } else {
2046 emit_gmrmi(as, XG_ARITHi(XOg_CMP), r64 + left, imm);
2047 }
2048 }
2049 } else {
2050 Reg left = ra_alloc1(as, lref, RSET_GPR);
2051 Reg right = asm_fuseload(as, rref, rset_exclude(RSET_GPR, left));
2052 asm_guardcc(as, cc);
2053 emit_mrm(as, XO_CMP, r64 + left, right);
2054 }
2055 }
2056}
2057
2058#if LJ_32 && LJ_HASFFI
2059/* 64 bit integer comparisons in 32 bit mode. */
2060static void asm_comp_int64(ASMState *as, IRIns *ir)
2061{
2062 uint32_t cc = asm_compmap[(ir-1)->o];
2063 RegSet allow = RSET_GPR;
2064 Reg lefthi = RID_NONE, leftlo = RID_NONE;
2065 Reg righthi = RID_NONE, rightlo = RID_NONE;
2066 MCLabel l_around;
2067 x86ModRM mrm;
2068
2069 as->curins--; /* Skip loword ins. Avoids failing in noconflict(), too. */
2070
2071 /* Allocate/fuse hiword operands. */
2072 if (irref_isk(ir->op2)) {
2073 lefthi = asm_fuseload(as, ir->op1, allow);
2074 } else {
2075 lefthi = ra_alloc1(as, ir->op1, allow);
2076 righthi = asm_fuseload(as, ir->op2, allow);
2077 if (righthi == RID_MRM) {
2078 if (as->mrm.base != RID_NONE) rset_clear(allow, as->mrm.base);
2079 if (as->mrm.idx != RID_NONE) rset_clear(allow, as->mrm.idx);
2080 } else {
2081 rset_clear(allow, righthi);
2082 }
2083 }
2084 mrm = as->mrm; /* Save state for hiword instruction. */
2085
2086 /* Allocate/fuse loword operands. */
2087 if (irref_isk((ir-1)->op2)) {
2088 leftlo = asm_fuseload(as, (ir-1)->op1, allow);
2089 } else {
2090 leftlo = ra_alloc1(as, (ir-1)->op1, allow);
2091 rightlo = asm_fuseload(as, (ir-1)->op2, allow);
2092 if (rightlo == RID_MRM) {
2093 if (as->mrm.base != RID_NONE) rset_clear(allow, as->mrm.base);
2094 if (as->mrm.idx != RID_NONE) rset_clear(allow, as->mrm.idx);
2095 } else {
2096 rset_clear(allow, rightlo);
2097 }
2098 }
2099
2100 /* All register allocations must be performed _before_ this point. */
2101 l_around = emit_label(as);
2102 as->invmcp = as->flagmcp = NULL; /* Cannot use these optimizations. */
2103
2104 /* Loword comparison and branch. */
2105 asm_guardcc(as, cc >> 4); /* Always use unsigned compare for loword. */
2106 if (ra_noreg(rightlo)) {
2107 int32_t imm = IR((ir-1)->op2)->i;
2108 if (imm == 0 && ((cc >> 4) & 0xa) != 0x2 && leftlo != RID_MRM)
2109 emit_rr(as, XO_TEST, leftlo, leftlo);
2110 else
2111 emit_gmrmi(as, XG_ARITHi(XOg_CMP), leftlo, imm);
2112 } else {
2113 emit_mrm(as, XO_CMP, leftlo, rightlo);
2114 }
2115
2116 /* Hiword comparison and branches. */
2117 if ((cc & 15) != CC_NE)
2118 emit_sjcc(as, CC_NE, l_around); /* Hiword unequal: skip loword compare. */
2119 if ((cc & 15) != CC_E)
2120 asm_guardcc(as, cc >> 8); /* Hiword compare without equality check. */
2121 as->mrm = mrm; /* Restore state. */
2122 if (ra_noreg(righthi)) {
2123 int32_t imm = IR(ir->op2)->i;
2124 if (imm == 0 && (cc & 0xa) != 0x2 && lefthi != RID_MRM)
2125 emit_rr(as, XO_TEST, lefthi, lefthi);
2126 else
2127 emit_gmrmi(as, XG_ARITHi(XOg_CMP), lefthi, imm);
2128 } else {
2129 emit_mrm(as, XO_CMP, lefthi, righthi);
2130 }
2131}
2132#endif
2133
2134/* -- Support for 64 bit ops in 32 bit mode ------------------------------- */
2135
2136/* Hiword op of a split 64 bit op. Previous op must be the loword op. */
2137static void asm_hiop(ASMState *as, IRIns *ir)
2138{
2139#if LJ_32 && LJ_HASFFI
2140 /* HIOP is marked as a store because it needs its own DCE logic. */
2141 int uselo = ra_used(ir-1), usehi = ra_used(ir); /* Loword/hiword used? */
2142 if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
2143 if ((ir-1)->o == IR_CONV) { /* Conversions to/from 64 bit. */
2144 if (usehi || uselo) {
2145 if (irt_isfp(ir->t))
2146 asm_conv_fp_int64(as, ir);
2147 else
2148 asm_conv_int64_fp(as, ir);
2149 }
2150 as->curins--; /* Always skip the CONV. */
2151 return;
2152 } else if ((ir-1)->o <= IR_NE) { /* 64 bit integer comparisons. ORDER IR. */
2153 asm_comp_int64(as, ir);
2154 return;
2155 }
2156 if (!usehi) return; /* Skip unused hiword op for all remaining ops. */
2157 switch ((ir-1)->o) {
2158 case IR_ADD:
2159 asm_intarith(as, ir, uselo ? XOg_ADC : XOg_ADD);
2160 break;
2161 case IR_SUB:
2162 asm_intarith(as, ir, uselo ? XOg_SBB : XOg_SUB);
2163 break;
2164 case IR_NEG: {
2165 Reg dest = ra_dest(as, ir, RSET_GPR);
2166 emit_rr(as, XO_GROUP3, XOg_NEG, dest);
2167 if (uselo) {
2168 emit_i8(as, 0);
2169 emit_rr(as, XO_ARITHi8, XOg_ADC, dest);
2170 }
2171 ra_left(as, dest, ir->op1);
2172 break;
2173 }
2174 case IR_CALLN:
2175 case IR_CALLXS:
2176 ra_destreg(as, ir, RID_RETHI);
2177 if (!uselo)
2178 ra_allocref(as, ir->op1, RID2RSET(RID_RET)); /* Mark call as used. */
2179 break;
2180 case IR_CNEWI:
2181 /* Nothing to do here. Handled by CNEWI itself. */
2182 break;
2183 default: lua_assert(0); break;
2184 }
2185#else
2186 UNUSED(as); UNUSED(ir); lua_assert(0); /* Unused on x64 or without FFI. */
2187#endif
2188}
2189
2190/* -- Stack handling ------------------------------------------------------ */
2191
2192/* Check Lua stack size for overflow. Use exit handler as fallback. */
2193static void asm_stack_check(ASMState *as, BCReg topslot,
2194 Reg pbase, RegSet allow, ExitNo exitno)
2195{
2196 /* Try to get an unused temp. register, otherwise spill/restore eax. */
2197 Reg r = allow ? rset_pickbot(allow) : RID_EAX;
2198 emit_jcc(as, CC_B, exitstub_addr(as->J, exitno));
2199 if (allow == RSET_EMPTY) /* Restore temp. register. */
2200 emit_rmro(as, XO_MOV, r|REX_64, RID_ESP, 0);
2201 else
2202 ra_modified(as, r);
2203 emit_gri(as, XG_ARITHi(XOg_CMP), r, (int32_t)(8*topslot));
2204 if (ra_hasreg(pbase) && pbase != r)
2205 emit_rr(as, XO_ARITH(XOg_SUB), r, pbase);
2206 else
2207 emit_rmro(as, XO_ARITH(XOg_SUB), r, RID_NONE,
2208 ptr2addr(&J2G(as->J)->jit_base));
2209 emit_rmro(as, XO_MOV, r, r, offsetof(lua_State, maxstack));
2210 emit_getgl(as, r, jit_L);
2211 if (allow == RSET_EMPTY) /* Spill temp. register. */
2212 emit_rmro(as, XO_MOVto, r|REX_64, RID_ESP, 0);
2213}
2214
2215/* Restore Lua stack from on-trace state. */
2216static void asm_stack_restore(ASMState *as, SnapShot *snap)
2217{
2218 SnapEntry *map = &as->T->snapmap[snap->mapofs];
2219 MSize n, nent = snap->nent;
2220 SnapEntry *flinks = map + nent + snap->depth;
2221 /* Store the value of all modified slots to the Lua stack. */
2222 for (n = 0; n < nent; n++) {
2223 SnapEntry sn = map[n];
2224 BCReg s = snap_slot(sn);
2225 int32_t ofs = 8*((int32_t)s-1);
2226 IRRef ref = snap_ref(sn);
2227 IRIns *ir = IR(ref);
2228 if ((sn & SNAP_NORESTORE))
2229 continue;
2230 if (irt_isnum(ir->t)) {
2231 Reg src = ra_alloc1(as, ref, RSET_FPR);
2232 emit_rmro(as, XO_MOVSDto, src, RID_BASE, ofs);
2233 } else {
2234 lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t) ||
2235 (LJ_DUALNUM && irt_isinteger(ir->t)));
2236 if (!irref_isk(ref)) {
2237 Reg src = ra_alloc1(as, ref, rset_exclude(RSET_GPR, RID_BASE));
2238 emit_movtomro(as, REX_64IR(ir, src), RID_BASE, ofs);
2239 } else if (!irt_ispri(ir->t)) {
2240 emit_movmroi(as, RID_BASE, ofs, ir->i);
2241 }
2242 if ((sn & (SNAP_CONT|SNAP_FRAME))) {
2243 if (s != 0) /* Do not overwrite link to previous frame. */
2244 emit_movmroi(as, RID_BASE, ofs+4, (int32_t)(*flinks--));
2245 } else {
2246 if (!(LJ_64 && irt_islightud(ir->t)))
2247 emit_movmroi(as, RID_BASE, ofs+4, irt_toitype(ir->t));
2248 }
2249 }
2250 checkmclim(as);
2251 }
2252 lua_assert(map + nent == flinks);
2253}
2254
2255/* -- GC handling --------------------------------------------------------- */
2256
2257/* Check GC threshold and do one or more GC steps. */
2258static void asm_gc_check(ASMState *as)
2259{
2260 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
2261 IRRef args[2];
2262 MCLabel l_end;
2263 Reg tmp;
2264 ra_evictset(as, RSET_SCRATCH);
2265 l_end = emit_label(as);
2266 /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
2267 asm_guardcc(as, CC_NE); /* Assumes asm_snap_prep() already done. */
2268 emit_rr(as, XO_TEST, RID_RET, RID_RET);
2269 args[0] = ASMREF_TMP1; /* global_State *g */
2270 args[1] = ASMREF_TMP2; /* MSize steps */
2271 asm_gencall(as, ci, args);
2272 tmp = ra_releasetmp(as, ASMREF_TMP1);
2273 emit_loada(as, tmp, J2G(as->J));
2274 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP2), (int32_t)as->gcsteps);
2275 /* Jump around GC step if GC total < GC threshold. */
2276 emit_sjcc(as, CC_B, l_end);
2277 emit_opgl(as, XO_ARITH(XOg_CMP), tmp, gc.threshold);
2278 emit_getgl(as, tmp, gc.total);
2279 as->gcsteps = 0;
2280 checkmclim(as);
2281}
2282
2283/* -- Loop handling ------------------------------------------------------- */
2284
2285/* Fixup the loop branch. */
2286static void asm_loop_fixup(ASMState *as)
2287{
2288 MCode *p = as->mctop;
2289 MCode *target = as->mcp;
2290 if (as->realign) { /* Realigned loops use short jumps. */
2291 as->realign = NULL; /* Stop another retry. */
2292 lua_assert(((intptr_t)target & 15) == 0);
2293 if (as->loopinv) { /* Inverted loop branch? */
2294 p -= 5;
2295 p[0] = XI_JMP;
2296 lua_assert(target - p >= -128);
2297 p[-1] = (MCode)(target - p); /* Patch sjcc. */
2298 if (as->loopinv == 2)
2299 p[-3] = (MCode)(target - p + 2); /* Patch opt. short jp. */
2300 } else {
2301 lua_assert(target - p >= -128);
2302 p[-1] = (MCode)(int8_t)(target - p); /* Patch short jmp. */
2303 p[-2] = XI_JMPs;
2304 }
2305 } else {
2306 MCode *newloop;
2307 p[-5] = XI_JMP;
2308 if (as->loopinv) { /* Inverted loop branch? */
2309 /* asm_guardcc already inverted the jcc and patched the jmp. */
2310 p -= 5;
2311 newloop = target+4;
2312 *(int32_t *)(p-4) = (int32_t)(target - p); /* Patch jcc. */
2313 if (as->loopinv == 2) {
2314 *(int32_t *)(p-10) = (int32_t)(target - p + 6); /* Patch opt. jp. */
2315 newloop = target+8;
2316 }
2317 } else { /* Otherwise just patch jmp. */
2318 *(int32_t *)(p-4) = (int32_t)(target - p);
2319 newloop = target+3;
2320 }
2321 /* Realign small loops and shorten the loop branch. */
2322 if (newloop >= p - 128) {
2323 as->realign = newloop; /* Force a retry and remember alignment. */
2324 as->curins = as->stopins; /* Abort asm_trace now. */
2325 as->T->nins = as->orignins; /* Remove any added renames. */
2326 }
2327 }
2328}
2329
2330/* -- Head of trace ------------------------------------------------------- */
2331
2332/* Coalesce BASE register for a root trace. */
2333static void asm_head_root_base(ASMState *as)
2334{
2335 IRIns *ir = IR(REF_BASE);
2336 Reg r = ir->r;
2337 if (ra_hasreg(r)) {
2338 ra_free(as, r);
2339 if (rset_test(as->modset, r))
2340 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
2341 if (r != RID_BASE)
2342 emit_rr(as, XO_MOV, r, RID_BASE);
2343 }
2344}
2345
2346/* Coalesce or reload BASE register for a side trace. */
2347static RegSet asm_head_side_base(ASMState *as, Reg pbase, RegSet allow)
2348{
2349 IRIns *ir = IR(REF_BASE);
2350 Reg r = ir->r;
2351 if (ra_hasreg(r)) {
2352 ra_free(as, r);
2353 if (rset_test(as->modset, r))
2354 ir->r = RID_INIT; /* No inheritance for modified BASE register. */
2355 if (pbase == r) {
2356 rset_clear(allow, r); /* Mark same BASE register as coalesced. */
2357 } else if (ra_hasreg(pbase) && rset_test(as->freeset, pbase)) {
2358 rset_clear(allow, pbase);
2359 emit_rr(as, XO_MOV, r, pbase); /* Move from coalesced parent register. */
2360 } else {
2361 emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
2362 }
2363 }
2364 return allow;
2365}
2366
2367/* -- Tail of trace ------------------------------------------------------- */
2368
2369/* Fixup the tail code. */
2370static void asm_tail_fixup(ASMState *as, TraceNo lnk)
2371{
2372 /* Note: don't use as->mcp swap + emit_*: emit_op overwrites more bytes. */
2373 MCode *p = as->mctop;
2374 MCode *target, *q;
2375 int32_t spadj = as->T->spadjust;
2376 if (spadj == 0) {
2377 p -= ((as->flags & JIT_F_LEA_AGU) ? 7 : 6) + (LJ_64 ? 1 : 0);
2378 } else {
2379 MCode *p1;
2380 /* Patch stack adjustment. */
2381 if (checki8(spadj)) {
2382 p -= 3;
2383 p1 = p-6;
2384 *p1 = (MCode)spadj;
2385 } else {
2386 p1 = p-9;
2387 *(int32_t *)p1 = spadj;
2388 }
2389 if ((as->flags & JIT_F_LEA_AGU)) {
2390#if LJ_64
2391 p1[-4] = 0x48;
2392#endif
2393 p1[-3] = (MCode)XI_LEA;
2394 p1[-2] = MODRM(checki8(spadj) ? XM_OFS8 : XM_OFS32, RID_ESP, RID_ESP);
2395 p1[-1] = MODRM(XM_SCALE1, RID_ESP, RID_ESP);
2396 } else {
2397#if LJ_64
2398 p1[-3] = 0x48;
2399#endif
2400 p1[-2] = (MCode)(checki8(spadj) ? XI_ARITHi8 : XI_ARITHi);
2401 p1[-1] = MODRM(XM_REG, XOg_ADD, RID_ESP);
2402 }
2403 }
2404 /* Patch exit branch. */
2405 target = lnk == TRACE_INTERP ? (MCode *)lj_vm_exit_interp :
2406 traceref(as->J, lnk)->mcode;
2407 *(int32_t *)(p-4) = jmprel(p, target);
2408 p[-5] = XI_JMP;
2409 /* Drop unused mcode tail. Fill with NOPs to make the prefetcher happy. */
2410 for (q = as->mctop-1; q >= p; q--)
2411 *q = XI_NOP;
2412 as->mctop = p;
2413}
2414
2415/* Prepare tail of code. */
2416static void asm_tail_prep(ASMState *as)
2417{
2418 MCode *p = as->mctop;
2419 /* Realign and leave room for backwards loop branch or exit branch. */
2420 if (as->realign) {
2421 int i = ((int)(intptr_t)as->realign) & 15;
2422 /* Fill unused mcode tail with NOPs to make the prefetcher happy. */
2423 while (i-- > 0)
2424 *--p = XI_NOP;
2425 as->mctop = p;
2426 p -= (as->loopinv ? 5 : 2); /* Space for short/near jmp. */
2427 } else {
2428 p -= 5; /* Space for exit branch (near jmp). */
2429 }
2430 if (as->loopref) {
2431 as->invmcp = as->mcp = p;
2432 } else {
2433 /* Leave room for ESP adjustment: add esp, imm or lea esp, [esp+imm] */
2434 as->mcp = p - (((as->flags & JIT_F_LEA_AGU) ? 7 : 6) + (LJ_64 ? 1 : 0));
2435 as->invmcp = NULL;
2436 }
2437}
2438
2439/* -- Instruction dispatch ------------------------------------------------ */
2440
2441/* Assemble a single instruction. */
2442static void asm_ir(ASMState *as, IRIns *ir)
2443{
2444 switch ((IROp)ir->o) {
2445 /* Miscellaneous ops. */
2446 case IR_LOOP: asm_loop(as); break;
2447 case IR_NOP: case IR_XBAR: lua_assert(!ra_used(ir)); break;
2448 case IR_USE:
2449 ra_alloc1(as, ir->op1, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR); break;
2450 case IR_PHI: asm_phi(as, ir); break;
2451 case IR_HIOP: asm_hiop(as, ir); break;
2452
2453 /* Guarded assertions. */
2454 case IR_LT: case IR_GE: case IR_LE: case IR_GT:
2455 case IR_ULT: case IR_UGE: case IR_ULE: case IR_UGT:
2456 case IR_EQ: case IR_NE: case IR_ABC:
2457 asm_comp(as, ir, asm_compmap[ir->o]);
2458 break;
2459
2460 case IR_RETF: asm_retf(as, ir); break;
2461
2462 /* Bit ops. */
2463 case IR_BNOT: asm_neg_not(as, ir, XOg_NOT); break;
2464 case IR_BSWAP: asm_bitswap(as, ir); break;
2465
2466 case IR_BAND: asm_intarith(as, ir, XOg_AND); break;
2467 case IR_BOR: asm_intarith(as, ir, XOg_OR); break;
2468 case IR_BXOR: asm_intarith(as, ir, XOg_XOR); break;
2469
2470 case IR_BSHL: asm_bitshift(as, ir, XOg_SHL); break;
2471 case IR_BSHR: asm_bitshift(as, ir, XOg_SHR); break;
2472 case IR_BSAR: asm_bitshift(as, ir, XOg_SAR); break;
2473 case IR_BROL: asm_bitshift(as, ir, XOg_ROL); break;
2474 case IR_BROR: asm_bitshift(as, ir, XOg_ROR); break;
2475
2476 /* Arithmetic ops. */
2477 case IR_ADD: asm_add(as, ir); break;
2478 case IR_SUB:
2479 if (irt_isnum(ir->t))
2480 asm_fparith(as, ir, XO_SUBSD);
2481 else /* Note: no need for LEA trick here. i-k is encoded as i+(-k). */
2482 asm_intarith(as, ir, XOg_SUB);
2483 break;
2484 case IR_MUL:
2485 if (irt_isnum(ir->t))
2486 asm_fparith(as, ir, XO_MULSD);
2487 else
2488 asm_intarith(as, ir, XOg_X_IMUL);
2489 break;
2490 case IR_DIV:
2491#if LJ_64 && LJ_HASFFI
2492 if (!irt_isnum(ir->t))
2493 asm_arith64(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_divi64 :
2494 IRCALL_lj_carith_divu64);
2495 else
2496#endif
2497 asm_fparith(as, ir, XO_DIVSD);
2498 break;
2499 case IR_MOD:
2500#if LJ_64 && LJ_HASFFI
2501 asm_arith64(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_modi64 :
2502 IRCALL_lj_carith_modu64);
2503#else
2504 lua_assert(0);
2505#endif
2506 break;
2507
2508 case IR_NEG:
2509 if (irt_isnum(ir->t))
2510 asm_fparith(as, ir, XO_XORPS);
2511 else
2512 asm_neg_not(as, ir, XOg_NEG);
2513 break;
2514 case IR_ABS: asm_fparith(as, ir, XO_ANDPS); break;
2515
2516 case IR_MIN:
2517 if (irt_isnum(ir->t))
2518 asm_fparith(as, ir, XO_MINSD);
2519 else
2520 asm_min_max(as, ir, CC_G);
2521 break;
2522 case IR_MAX:
2523 if (irt_isnum(ir->t))
2524 asm_fparith(as, ir, XO_MAXSD);
2525 else
2526 asm_min_max(as, ir, CC_L);
2527 break;
2528
2529 case IR_FPMATH: case IR_ATAN2: case IR_LDEXP:
2530 asm_fpmath(as, ir);
2531 break;
2532 case IR_POW:
2533#if LJ_64 && LJ_HASFFI
2534 if (!irt_isnum(ir->t))
2535 asm_arith64(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_powi64 :
2536 IRCALL_lj_carith_powu64);
2537 else
2538#endif
2539 asm_fppowi(as, ir);
2540 break;
2541
2542 /* Overflow-checking arithmetic ops. Note: don't use LEA here! */
2543 case IR_ADDOV: asm_intarith(as, ir, XOg_ADD); break;
2544 case IR_SUBOV: asm_intarith(as, ir, XOg_SUB); break;
2545 case IR_MULOV: asm_intarith(as, ir, XOg_X_IMUL); break;
2546
2547 /* Memory references. */
2548 case IR_AREF: asm_aref(as, ir); break;
2549 case IR_HREF: asm_href(as, ir); break;
2550 case IR_HREFK: asm_hrefk(as, ir); break;
2551 case IR_NEWREF: asm_newref(as, ir); break;
2552 case IR_UREFO: case IR_UREFC: asm_uref(as, ir); break;
2553 case IR_FREF: asm_fref(as, ir); break;
2554 case IR_STRREF: asm_strref(as, ir); break;
2555
2556 /* Loads and stores. */
2557 case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
2558 asm_ahuvload(as, ir);
2559 break;
2560 case IR_FLOAD: case IR_XLOAD: asm_fxload(as, ir); break;
2561 case IR_SLOAD: asm_sload(as, ir); break;
2562
2563 case IR_ASTORE: case IR_HSTORE: case IR_USTORE: asm_ahustore(as, ir); break;
2564 case IR_FSTORE: case IR_XSTORE: asm_fxstore(as, ir); break;
2565
2566 /* Allocations. */
2567 case IR_SNEW: case IR_XSNEW: asm_snew(as, ir); break;
2568 case IR_TNEW: asm_tnew(as, ir); break;
2569 case IR_TDUP: asm_tdup(as, ir); break;
2570 case IR_CNEW: case IR_CNEWI: asm_cnew(as, ir); break;
2571
2572 /* Write barriers. */
2573 case IR_TBAR: asm_tbar(as, ir); break;
2574 case IR_OBAR: asm_obar(as, ir); break;
2575
2576 /* Type conversions. */
2577 case IR_TOBIT: asm_tobit(as, ir); break;
2578 case IR_CONV: asm_conv(as, ir); break;
2579 case IR_TOSTR: asm_tostr(as, ir); break;
2580 case IR_STRTO: asm_strto(as, ir); break;
2581
2582 /* Calls. */
2583 case IR_CALLN: case IR_CALLL: case IR_CALLS: asm_call(as, ir); break;
2584 case IR_CALLXS: asm_callx(as, ir); break;
2585 case IR_CARG: break;
2586
2587 default:
2588 setintV(&as->J->errinfo, ir->o);
2589 lj_trace_err_info(as->J, LJ_TRERR_NYIIR);
2590 break;
2591 }
2592}
2593
2594/* -- Trace setup --------------------------------------------------------- */
2595
2596/* Ensure there are enough stack slots for call arguments. */
2597static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
2598{
2599 IRRef args[CCI_NARGS_MAX];
2600 uint32_t nargs = (int)CCI_NARGS(ci);
2601 int nslots = 0;
2602 asm_collectargs(as, ir, ci, args);
2603#if LJ_64
2604 if (LJ_ABI_WIN) {
2605 nslots = (int)(nargs*2); /* Only matters for more than four args. */
2606 } else {
2607 uint32_t i;
2608 int ngpr = 6, nfpr = 8;
2609 for (i = 0; i < nargs; i++)
2610 if (irt_isfp(IR(args[i])->t)) {
2611 if (nfpr > 0) nfpr--; else nslots += 2;
2612 } else {
2613 if (ngpr > 0) ngpr--; else nslots += 2;
2614 }
2615 }
2616 if (nslots > as->evenspill) /* Leave room for args in stack slots. */
2617 as->evenspill = nslots;
2618 return irt_isfp(ir->t) ? REGSP_HINT(RID_FPRET) : REGSP_HINT(RID_RET);
2619#else
2620 if ((ci->flags & CCI_FASTCALL)) {
2621 lua_assert(nargs <= 2);
2622 } else {
2623 uint32_t i;
2624 for (i = 0; i < nargs; i++)
2625 nslots += irt_isnum(IR(args[i])->t) ? 2 : 1;
2626 if (nslots > as->evenspill) /* Leave room for args. */
2627 as->evenspill = nslots;
2628 }
2629 return irt_isfp(ir->t) ? REGSP_INIT : REGSP_HINT(RID_RET);
2630#endif
2631}
2632
2633/* Target-specific setup. */
2634static void asm_setup_target(ASMState *as)
2635{
2636 asm_exitstub_setup(as, as->T->nsnap);
2637}
2638
2639/* -- Trace patching ------------------------------------------------------ */
2640
2641/* Patch exit jumps of existing machine code to a new target. */
2642void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
2643{
2644 MCode *p = T->mcode;
2645 MCode *mcarea = lj_mcode_patch(J, p, 0);
2646 MSize len = T->szmcode;
2647 MCode *px = exitstub_addr(J, exitno) - 6;
2648 MCode *pe = p+len-6;
2649 uint32_t stateaddr = u32ptr(&J2G(J)->vmstate);
2650 if (len > 5 && p[len-5] == XI_JMP && p+len-6 + *(int32_t *)(p+len-4) == px)
2651 *(int32_t *)(p+len-4) = jmprel(p+len, target);
2652 /* Do not patch parent exit for a stack check. Skip beyond vmstate update. */
2653 for (; p < pe; p++)
2654 if (*(uint32_t *)(p+(LJ_64 ? 3 : 2)) == stateaddr && p[0] == XI_MOVmi) {
2655 p += LJ_64 ? 11 : 10;
2656 break;
2657 }
2658 lua_assert(p < pe);
2659 for (; p < pe; p++) {
2660 if ((*(uint16_t *)p & 0xf0ff) == 0x800f && p + *(int32_t *)(p+2) == px) {
2661 *(int32_t *)(p+2) = jmprel(p+6, target);
2662 p += 5;
2663 }
2664 }
2665 lj_mcode_patch(J, mcarea, 1);
2666 VG_INVALIDATE(T->mcode, T->szmcode);
2667}
2668
generated by cgit v1.2.3-55-g6feb (git 2.39.1) at 2025-08-10 16:03:46 +0000