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Diffstat (limited to 'src/lj_target_arm.h')
-rw-r--r-- | src/lj_target_arm.h | 205 |
1 files changed, 205 insertions, 0 deletions
diff --git a/src/lj_target_arm.h b/src/lj_target_arm.h new file mode 100644 index 00000000..78a5679d --- /dev/null +++ b/src/lj_target_arm.h | |||
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1 | /* | ||
2 | ** Definitions for ARM CPUs. | ||
3 | ** Copyright (C) 2005-2011 Mike Pall. See Copyright Notice in luajit.h | ||
4 | */ | ||
5 | |||
6 | #ifndef _LJ_TARGET_ARM_H | ||
7 | #define _LJ_TARGET_ARM_H | ||
8 | |||
9 | /* -- Registers IDs ------------------------------------------------------- */ | ||
10 | |||
11 | #define GPRDEF(_) \ | ||
12 | _(R0) _(R1) _(R2) _(R3) _(R4) _(R5) _(R6) _(R7) \ | ||
13 | _(R8) _(R9) _(R10) _(R11) _(R12) _(SP) _(LR) _(PC) | ||
14 | #if LJ_SOFTFP | ||
15 | #define FPRDEF(_) | ||
16 | #else | ||
17 | #error "NYI: hard-float support for ARM" | ||
18 | #endif | ||
19 | #define VRIDDEF(_) | ||
20 | |||
21 | #define RIDENUM(name) RID_##name, | ||
22 | |||
23 | enum { | ||
24 | GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */ | ||
25 | FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */ | ||
26 | RID_MAX, | ||
27 | RID_TMP = RID_LR, | ||
28 | |||
29 | /* Calling conventions. */ | ||
30 | RID_RET = RID_R0, | ||
31 | RID_RETHI = RID_R1, | ||
32 | RID_FPRET = RID_R0, | ||
33 | |||
34 | /* These definitions must match with the *.dasc file(s): */ | ||
35 | RID_BASE = RID_R9, /* Interpreter BASE. */ | ||
36 | RID_LPC = RID_R6, /* Interpreter PC. */ | ||
37 | RID_DISPATCH = RID_R7, /* Interpreter DISPATCH table. */ | ||
38 | RID_LREG = RID_R8, /* Interpreter L. */ | ||
39 | |||
40 | /* Register ranges [min, max) and number of registers. */ | ||
41 | RID_MIN_GPR = RID_R0, | ||
42 | RID_MAX_GPR = RID_PC+1, | ||
43 | RID_MIN_FPR = RID_MAX_GPR, | ||
44 | #if LJ_SOFTFP | ||
45 | RID_MAX_FPR = RID_MIN_FPR, | ||
46 | #else | ||
47 | #error "NYI: VFP support for ARM" | ||
48 | #endif | ||
49 | RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR, | ||
50 | RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR | ||
51 | }; | ||
52 | |||
53 | #define RID_NUM_KREF RID_NUM_GPR | ||
54 | #define RID_MIN_KREF RID_R0 | ||
55 | |||
56 | /* -- Register sets ------------------------------------------------------- */ | ||
57 | |||
58 | /* Make use of all registers, except sp, lr and pc. */ | ||
59 | #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_R12+1)) | ||
60 | #define RSET_GPREVEN \ | ||
61 | (RID2RSET(RID_R0)|RID2RSET(RID_R2)|RID2RSET(RID_R4)|RID2RSET(RID_R6)| \ | ||
62 | RID2RSET(RID_R8)|RID2RSET(RID_R10)) | ||
63 | #define RSET_GPRODD \ | ||
64 | (RID2RSET(RID_R1)|RID2RSET(RID_R3)|RID2RSET(RID_R5)|RID2RSET(RID_R7)| \ | ||
65 | RID2RSET(RID_R9)|RID2RSET(RID_R11)) | ||
66 | #if LJ_SOFTFP | ||
67 | #define RSET_FPR 0 | ||
68 | #define RSET_ALL RSET_GPR | ||
69 | #else | ||
70 | #error "NYI: VFP support for ARM" | ||
71 | #endif | ||
72 | #define RSET_INIT RSET_ALL | ||
73 | |||
74 | /* ABI-specific register sets. lr is an implicit scratch register. */ | ||
75 | #define RSET_SCRATCH_GPR_ (RSET_RANGE(RID_R0, RID_R3+1)|RID2RSET(RID_R12)) | ||
76 | #ifdef __APPLE__ | ||
77 | #define RSET_SCRATCH_GPR (RSET_SCRATCH_GPR_|RID2RSET(RID_R9)) | ||
78 | #else | ||
79 | #define RSET_SCRATCH_GPR RSET_SCRATCH_GPR_ | ||
80 | #endif | ||
81 | #if LJ_SOFTFP | ||
82 | #define RSET_SCRATCH_FPR 0 | ||
83 | #else | ||
84 | #error "NYI: VFP support for ARM" | ||
85 | #endif | ||
86 | #define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR) | ||
87 | #define REGARG_FIRSTGPR RID_R0 | ||
88 | #define REGARG_LASTGPR RID_R3 | ||
89 | #define REGARG_NUMGPR 4 | ||
90 | |||
91 | /* -- Spill slots --------------------------------------------------------- */ | ||
92 | |||
93 | /* Spill slots are 32 bit wide. An even/odd pair is used for FPRs. | ||
94 | ** | ||
95 | ** SPS_FIXED: Available fixed spill slots in interpreter frame. | ||
96 | ** This definition must match with the *.dasc file(s). | ||
97 | ** | ||
98 | ** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots. | ||
99 | */ | ||
100 | #define SPS_FIXED 2 | ||
101 | #define SPS_FIRST 2 | ||
102 | |||
103 | #define sps_scale(slot) (4 * (int32_t)(slot)) | ||
104 | #define sps_align(slot) (((slot) - SPS_FIXED + 1) & ~1) | ||
105 | |||
106 | /* -- Exit state ---------------------------------------------------------- */ | ||
107 | |||
108 | /* This definition must match with the *.dasc file(s). */ | ||
109 | typedef struct { | ||
110 | #if !LJ_SOFTFP | ||
111 | lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */ | ||
112 | #endif | ||
113 | int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */ | ||
114 | int32_t spill[256]; /* Spill slots. */ | ||
115 | } ExitState; | ||
116 | |||
117 | /* PC after instruction that caused an exit. Used to find the trace number. */ | ||
118 | #define EXITSTATE_PCREG RID_PC | ||
119 | |||
120 | #define EXITSTUB_SPACING 4 | ||
121 | #define EXITSTUBS_PER_GROUP 32 | ||
122 | |||
123 | /* -- Instructions -------------------------------------------------------- */ | ||
124 | |||
125 | /* Instruction fields. */ | ||
126 | #define ARMF_CC(ai, cc) (((ai) ^ ARMI_CCAL) | ((cc) << 28)) | ||
127 | #define ARMF_N(r) ((r) << 16) | ||
128 | #define ARMF_D(r) ((r) << 12) | ||
129 | #define ARMF_S(r) ((r) << 8) | ||
130 | #define ARMF_M(r) (r) | ||
131 | #define ARMF_SH(sh, n) (((sh) << 5) | ((n) << 7)) | ||
132 | #define ARMF_RSH(sh, r) (0x10 | ((sh) << 5) | ARMF_S(r)) | ||
133 | |||
134 | typedef enum ARMIns { | ||
135 | ARMI_CCAL = 0xe0000000, | ||
136 | ARMI_S = 0x000100000, | ||
137 | ARMI_K12 = 0x02000000, | ||
138 | ARMI_KNEG = 0x00200000, | ||
139 | ARMI_LS_U = 0x00800000, | ||
140 | ARMI_LS_P = 0x01000000, | ||
141 | ARMI_LS_R = 0x02000000, | ||
142 | ARMI_LSX_I = 0x00400000, | ||
143 | |||
144 | ARMI_AND = 0xe0000000, | ||
145 | ARMI_EOR = 0xe0200000, | ||
146 | ARMI_SUB = 0xe0400000, | ||
147 | ARMI_RSB = 0xe0600000, | ||
148 | ARMI_ADD = 0xe0800000, | ||
149 | ARMI_ADC = 0xe0a00000, | ||
150 | ARMI_SBC = 0xe0c00000, | ||
151 | ARMI_RSC = 0xe0e00000, | ||
152 | ARMI_TST = 0xe1100000, | ||
153 | ARMI_TEQ = 0xe1300000, | ||
154 | ARMI_CMP = 0xe1500000, | ||
155 | ARMI_CMN = 0xe1700000, | ||
156 | ARMI_ORR = 0xe1800000, | ||
157 | ARMI_MOV = 0xe1a00000, | ||
158 | ARMI_BIC = 0xe1c00000, | ||
159 | ARMI_MVN = 0xe1e00000, | ||
160 | |||
161 | ARMI_NOP = 0xe1a00000, | ||
162 | |||
163 | ARMI_MUL = 0xe0000090, | ||
164 | ARMI_SMULL = 0xe0c00090, | ||
165 | |||
166 | ARMI_LDR = 0xe4100000, | ||
167 | ARMI_LDRB = 0xe4500000, | ||
168 | ARMI_LDRH = 0xe01000b0, | ||
169 | ARMI_LDRSB = 0xe01000d0, | ||
170 | ARMI_LDRSH = 0xe01000f0, | ||
171 | ARMI_LDRD = 0xe00000d0, | ||
172 | ARMI_STR = 0xe4000000, | ||
173 | ARMI_STRB = 0xe4400000, | ||
174 | ARMI_STRH = 0xe00000b0, | ||
175 | ARMI_STRD = 0xe00000f0, | ||
176 | |||
177 | ARMI_B = 0xea000000, | ||
178 | ARMI_BL = 0xeb000000, | ||
179 | ARMI_BLX = 0xfa000000, | ||
180 | ARMI_BLXr = 0xe12fff30, | ||
181 | |||
182 | /* ARMv6 */ | ||
183 | ARMI_REV = 0xe6bf0f30, | ||
184 | ARMI_SXTB = 0xe6af0070, | ||
185 | ARMI_SXTH = 0xe6bf0070, | ||
186 | ARMI_UXTB = 0xe6ef0070, | ||
187 | ARMI_UXTH = 0xe6ff0070, | ||
188 | |||
189 | /* ARMv6T2 */ | ||
190 | ARMI_MOVW = 0xe3000000, | ||
191 | ARMI_MOVT = 0xe3400000, | ||
192 | } ARMIns; | ||
193 | |||
194 | typedef enum ARMShift { | ||
195 | ARMSH_LSL, ARMSH_LSR, ARMSH_ASR, ARMSH_ROR | ||
196 | } ARMShift; | ||
197 | |||
198 | /* ARM condition codes. */ | ||
199 | typedef enum ARMCC { | ||
200 | CC_EQ, CC_NE, CC_CS, CC_CC, CC_MI, CC_PL, CC_VS, CC_VC, | ||
201 | CC_HI, CC_LS, CC_GE, CC_LT, CC_GT, CC_LE, CC_AL, | ||
202 | CC_HS = CC_CS, CC_LO = CC_CC | ||
203 | } ARMCC; | ||
204 | |||
205 | #endif | ||