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-rw-r--r--src/lj_target_mips.h33
1 files changed, 32 insertions, 1 deletions
diff --git a/src/lj_target_mips.h b/src/lj_target_mips.h
index 67f3c003..bafa817a 100644
--- a/src/lj_target_mips.h
+++ b/src/lj_target_mips.h
@@ -13,11 +13,15 @@
13 _(R8) _(R9) _(R10) _(R11) _(R12) _(R13) _(R14) _(R15) \ 13 _(R8) _(R9) _(R10) _(R11) _(R12) _(R13) _(R14) _(R15) \
14 _(R16) _(R17) _(R18) _(R19) _(R20) _(R21) _(R22) _(R23) \ 14 _(R16) _(R17) _(R18) _(R19) _(R20) _(R21) _(R22) _(R23) \
15 _(R24) _(R25) _(SYS1) _(SYS2) _(R28) _(SP) _(R30) _(RA) 15 _(R24) _(R25) _(SYS1) _(SYS2) _(R28) _(SP) _(R30) _(RA)
16#if LJ_SOFTFP
17#define FPRDEF(_)
18#else
16#define FPRDEF(_) \ 19#define FPRDEF(_) \
17 _(F0) _(F1) _(F2) _(F3) _(F4) _(F5) _(F6) _(F7) \ 20 _(F0) _(F1) _(F2) _(F3) _(F4) _(F5) _(F6) _(F7) \
18 _(F8) _(F9) _(F10) _(F11) _(F12) _(F13) _(F14) _(F15) \ 21 _(F8) _(F9) _(F10) _(F11) _(F12) _(F13) _(F14) _(F15) \
19 _(F16) _(F17) _(F18) _(F19) _(F20) _(F21) _(F22) _(F23) \ 22 _(F16) _(F17) _(F18) _(F19) _(F20) _(F21) _(F22) _(F23) \
20 _(F24) _(F25) _(F26) _(F27) _(F28) _(F29) _(F30) _(F31) 23 _(F24) _(F25) _(F26) _(F27) _(F28) _(F29) _(F30) _(F31)
24#endif
21#define VRIDDEF(_) 25#define VRIDDEF(_)
22 26
23#define RIDENUM(name) RID_##name, 27#define RIDENUM(name) RID_##name,
@@ -38,7 +42,11 @@ enum {
38 RID_RETHI = RID_R2, 42 RID_RETHI = RID_R2,
39 RID_RETLO = RID_R3, 43 RID_RETLO = RID_R3,
40#endif 44#endif
45#if LJ_SOFTFP
46 RID_FPRET = RID_R2,
47#else
41 RID_FPRET = RID_F0, 48 RID_FPRET = RID_F0,
49#endif
42 RID_CFUNCADDR = RID_R25, 50 RID_CFUNCADDR = RID_R25,
43 51
44 /* These definitions must match with the *.dasc file(s): */ 52 /* These definitions must match with the *.dasc file(s): */
@@ -51,8 +59,12 @@ enum {
51 /* Register ranges [min, max) and number of registers. */ 59 /* Register ranges [min, max) and number of registers. */
52 RID_MIN_GPR = RID_R0, 60 RID_MIN_GPR = RID_R0,
53 RID_MAX_GPR = RID_RA+1, 61 RID_MAX_GPR = RID_RA+1,
54 RID_MIN_FPR = RID_F0, 62 RID_MIN_FPR = RID_MAX_GPR,
63#if LJ_SOFTFP
64 RID_MAX_FPR = RID_MIN_FPR,
65#else
55 RID_MAX_FPR = RID_F31+1, 66 RID_MAX_FPR = RID_F31+1,
67#endif
56 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR, 68 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
57 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR /* Only even regs are used. */ 69 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR /* Only even regs are used. */
58}; 70};
@@ -67,28 +79,42 @@ enum {
67 (RID2RSET(RID_ZERO)|RID2RSET(RID_TMP)|RID2RSET(RID_SP)|\ 79 (RID2RSET(RID_ZERO)|RID2RSET(RID_TMP)|RID2RSET(RID_SP)|\
68 RID2RSET(RID_SYS1)|RID2RSET(RID_SYS2)|RID2RSET(RID_JGL)) 80 RID2RSET(RID_SYS1)|RID2RSET(RID_SYS2)|RID2RSET(RID_JGL))
69#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED) 81#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED)
82#if LJ_SOFTFP
83#define RSET_FPR 0
84#else
70#define RSET_FPR \ 85#define RSET_FPR \
71 (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\ 86 (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\
72 RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\ 87 RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\
73 RID2RSET(RID_F16)|RID2RSET(RID_F18)|RID2RSET(RID_F20)|RID2RSET(RID_F22)|\ 88 RID2RSET(RID_F16)|RID2RSET(RID_F18)|RID2RSET(RID_F20)|RID2RSET(RID_F22)|\
74 RID2RSET(RID_F24)|RID2RSET(RID_F26)|RID2RSET(RID_F28)|RID2RSET(RID_F30)) 89 RID2RSET(RID_F24)|RID2RSET(RID_F26)|RID2RSET(RID_F28)|RID2RSET(RID_F30))
90#endif
75#define RSET_ALL (RSET_GPR|RSET_FPR) 91#define RSET_ALL (RSET_GPR|RSET_FPR)
76#define RSET_INIT RSET_ALL 92#define RSET_INIT RSET_ALL
77 93
78#define RSET_SCRATCH_GPR \ 94#define RSET_SCRATCH_GPR \
79 (RSET_RANGE(RID_R1, RID_R15+1)|\ 95 (RSET_RANGE(RID_R1, RID_R15+1)|\
80 RID2RSET(RID_R24)|RID2RSET(RID_R25)|RID2RSET(RID_R28)) 96 RID2RSET(RID_R24)|RID2RSET(RID_R25)|RID2RSET(RID_R28))
97#if LJ_SOFTFP
98#define RSET_SCRATCH_FPR 0
99#else
81#define RSET_SCRATCH_FPR \ 100#define RSET_SCRATCH_FPR \
82 (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\ 101 (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\
83 RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\ 102 RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\
84 RID2RSET(RID_F16)|RID2RSET(RID_F18)) 103 RID2RSET(RID_F16)|RID2RSET(RID_F18))
104#endif
85#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR) 105#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
86#define REGARG_FIRSTGPR RID_R4 106#define REGARG_FIRSTGPR RID_R4
87#define REGARG_LASTGPR RID_R7 107#define REGARG_LASTGPR RID_R7
88#define REGARG_NUMGPR 4 108#define REGARG_NUMGPR 4
109#if LJ_ABI_SOFTFP
110#define REGARG_FIRSTFPR 0
111#define REGARG_LASTFPR 0
112#define REGARG_NUMFPR 0
113#else
89#define REGARG_FIRSTFPR RID_F12 114#define REGARG_FIRSTFPR RID_F12
90#define REGARG_LASTFPR RID_F14 115#define REGARG_LASTFPR RID_F14
91#define REGARG_NUMFPR 2 116#define REGARG_NUMFPR 2
117#endif
92 118
93/* -- Spill slots --------------------------------------------------------- */ 119/* -- Spill slots --------------------------------------------------------- */
94 120
@@ -111,7 +137,9 @@ enum {
111 137
112/* This definition must match with the *.dasc file(s). */ 138/* This definition must match with the *.dasc file(s). */
113typedef struct { 139typedef struct {
140#if !LJ_SOFTFP
114 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */ 141 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
142#endif
115 int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */ 143 int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
116 int32_t spill[256]; /* Spill slots. */ 144 int32_t spill[256]; /* Spill slots. */
117} ExitState; 145} ExitState;
@@ -169,6 +197,9 @@ typedef enum MIPSIns {
169 MIPSI_SLTU = 0x0000002b, 197 MIPSI_SLTU = 0x0000002b,
170 MIPSI_MOVZ = 0x0000000a, 198 MIPSI_MOVZ = 0x0000000a,
171 MIPSI_MOVN = 0x0000000b, 199 MIPSI_MOVN = 0x0000000b,
200 MIPSI_MFHI = 0x00000010,
201 MIPSI_MFLO = 0x00000012,
202 MIPSI_MULT = 0x00000018,
172 203
173 MIPSI_SLL = 0x00000000, 204 MIPSI_SLL = 0x00000000,
174 MIPSI_SRL = 0x00000002, 205 MIPSI_SRL = 0x00000002,