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Diffstat (limited to 'src/lj_target_x86.h')
-rw-r--r--src/lj_target_x86.h41
1 files changed, 28 insertions, 13 deletions
diff --git a/src/lj_target_x86.h b/src/lj_target_x86.h
index 69aec37c..69cb8ca5 100644
--- a/src/lj_target_x86.h
+++ b/src/lj_target_x86.h
@@ -22,7 +22,7 @@
22 _(XMM0) _(XMM1) _(XMM2) _(XMM3) _(XMM4) _(XMM5) _(XMM6) _(XMM7) 22 _(XMM0) _(XMM1) _(XMM2) _(XMM3) _(XMM4) _(XMM5) _(XMM6) _(XMM7)
23#endif 23#endif
24#define VRIDDEF(_) \ 24#define VRIDDEF(_) \
25 _(MRM) 25 _(MRM) _(RIP)
26 26
27#define RIDENUM(name) RID_##name, 27#define RIDENUM(name) RID_##name,
28 28
@@ -31,15 +31,16 @@ enum {
31 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */ 31 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
32 RID_MAX, 32 RID_MAX,
33 RID_MRM = RID_MAX, /* Pseudo-id for ModRM operand. */ 33 RID_MRM = RID_MAX, /* Pseudo-id for ModRM operand. */
34 RID_RIP = RID_MAX+5, /* Pseudo-id for RIP (x64 only), rm bits = 5. */
34 35
35 /* Calling conventions. */ 36 /* Calling conventions. */
37 RID_SP = RID_ESP,
36 RID_RET = RID_EAX, 38 RID_RET = RID_EAX,
37#if LJ_64 39#if LJ_64
38 RID_FPRET = RID_XMM0, 40 RID_FPRET = RID_XMM0,
39#else 41#endif
40 RID_RETLO = RID_EAX, 42 RID_RETLO = RID_EAX,
41 RID_RETHI = RID_EDX, 43 RID_RETHI = RID_EDX,
42#endif
43 44
44 /* These definitions must match with the *.dasc file(s): */ 45 /* These definitions must match with the *.dasc file(s): */
45 RID_BASE = RID_EDX, /* Interpreter BASE. */ 46 RID_BASE = RID_EDX, /* Interpreter BASE. */
@@ -62,8 +63,10 @@ enum {
62 63
63/* -- Register sets ------------------------------------------------------- */ 64/* -- Register sets ------------------------------------------------------- */
64 65
65/* Make use of all registers, except the stack pointer. */ 66/* Make use of all registers, except the stack pointer (and maybe DISPATCH). */
66#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR)-RID2RSET(RID_ESP)) 67#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) \
68 - RID2RSET(RID_ESP) \
69 - LJ_GC64*RID2RSET(RID_DISPATCH))
67#define RSET_FPR (RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR)) 70#define RSET_FPR (RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR))
68#define RSET_ALL (RSET_GPR|RSET_FPR) 71#define RSET_ALL (RSET_GPR|RSET_FPR)
69#define RSET_INIT RSET_ALL 72#define RSET_INIT RSET_ALL
@@ -131,7 +134,11 @@ enum {
131#define SPS_FIXED (4*2) 134#define SPS_FIXED (4*2)
132#define SPS_FIRST (4*2) /* Don't use callee register save area. */ 135#define SPS_FIRST (4*2) /* Don't use callee register save area. */
133#else 136#else
137#if LJ_GC64
138#define SPS_FIXED 2
139#else
134#define SPS_FIXED 4 140#define SPS_FIXED 4
141#endif
135#define SPS_FIRST 2 142#define SPS_FIRST 2
136#endif 143#endif
137#else 144#else
@@ -157,6 +164,8 @@ typedef struct {
157#define EXITSTUB_SPACING (2+2) 164#define EXITSTUB_SPACING (2+2)
158#define EXITSTUBS_PER_GROUP 32 165#define EXITSTUBS_PER_GROUP 32
159 166
167#define EXITTRACE_VMSTATE 1 /* g->vmstate has traceno on exit. */
168
160/* -- x86 ModRM operand encoding ------------------------------------------ */ 169/* -- x86 ModRM operand encoding ------------------------------------------ */
161 170
162typedef enum { 171typedef enum {
@@ -184,12 +193,18 @@ typedef struct {
184#define XO_f20f(o) ((uint32_t)(0x0ff2fc + (0x##o<<24))) 193#define XO_f20f(o) ((uint32_t)(0x0ff2fc + (0x##o<<24)))
185#define XO_f30f(o) ((uint32_t)(0x0ff3fc + (0x##o<<24))) 194#define XO_f30f(o) ((uint32_t)(0x0ff3fc + (0x##o<<24)))
186 195
196#define XV_660f38(o) ((uint32_t)(0x79e2c4 + (0x##o<<24)))
197#define XV_f20f38(o) ((uint32_t)(0x7be2c4 + (0x##o<<24)))
198#define XV_f20f3a(o) ((uint32_t)(0x7be3c4 + (0x##o<<24)))
199#define XV_f30f38(o) ((uint32_t)(0x7ae2c4 + (0x##o<<24)))
200
187/* This list of x86 opcodes is not intended to be complete. Opcodes are only 201/* This list of x86 opcodes is not intended to be complete. Opcodes are only
188** included when needed. Take a look at DynASM or jit.dis_x86 to see the 202** included when needed. Take a look at DynASM or jit.dis_x86 to see the
189** whole mess. 203** whole mess.
190*/ 204*/
191typedef enum { 205typedef enum {
192 /* Fixed length opcodes. XI_* prefix. */ 206 /* Fixed length opcodes. XI_* prefix. */
207 XI_O16 = 0x66,
193 XI_NOP = 0x90, 208 XI_NOP = 0x90,
194 XI_XCHGa = 0x90, 209 XI_XCHGa = 0x90,
195 XI_CALL = 0xe8, 210 XI_CALL = 0xe8,
@@ -207,26 +222,28 @@ typedef enum {
207 XI_PUSHi8 = 0x6a, 222 XI_PUSHi8 = 0x6a,
208 XI_TESTb = 0x84, 223 XI_TESTb = 0x84,
209 XI_TEST = 0x85, 224 XI_TEST = 0x85,
225 XI_INT3 = 0xcc,
210 XI_MOVmi = 0xc7, 226 XI_MOVmi = 0xc7,
211 XI_GROUP5 = 0xff, 227 XI_GROUP5 = 0xff,
212 228
213 /* Note: little-endian byte-order! */ 229 /* Note: little-endian byte-order! */
214 XI_FLDZ = 0xeed9, 230 XI_FLDZ = 0xeed9,
215 XI_FLD1 = 0xe8d9, 231 XI_FLD1 = 0xe8d9,
216 XI_FLDLG2 = 0xecd9,
217 XI_FLDLN2 = 0xedd9,
218 XI_FDUP = 0xc0d9, /* Really fld st0. */ 232 XI_FDUP = 0xc0d9, /* Really fld st0. */
219 XI_FPOP = 0xd8dd, /* Really fstp st0. */ 233 XI_FPOP = 0xd8dd, /* Really fstp st0. */
220 XI_FPOP1 = 0xd9dd, /* Really fstp st1. */ 234 XI_FPOP1 = 0xd9dd, /* Really fstp st1. */
221 XI_FRNDINT = 0xfcd9, 235 XI_FRNDINT = 0xfcd9,
222 XI_FSIN = 0xfed9,
223 XI_FCOS = 0xffd9,
224 XI_FPTAN = 0xf2d9,
225 XI_FPATAN = 0xf3d9,
226 XI_FSCALE = 0xfdd9, 236 XI_FSCALE = 0xfdd9,
227 XI_FYL2X = 0xf1d9, 237 XI_FYL2X = 0xf1d9,
228 238
239 /* VEX-encoded instructions. XV_* prefix. */
240 XV_RORX = XV_f20f3a(f0),
241 XV_SARX = XV_f30f38(f7),
242 XV_SHLX = XV_660f38(f7),
243 XV_SHRX = XV_f20f38(f7),
244
229 /* Variable-length opcodes. XO_* prefix. */ 245 /* Variable-length opcodes. XO_* prefix. */
246 XO_OR = XO_(0b),
230 XO_MOV = XO_(8b), 247 XO_MOV = XO_(8b),
231 XO_MOVto = XO_(89), 248 XO_MOVto = XO_(89),
232 XO_MOVtow = XO_66(89), 249 XO_MOVtow = XO_66(89),
@@ -277,10 +294,8 @@ typedef enum {
277 XO_ROUNDSD = 0x0b3a0ffc, /* Really 66 0f 3a 0b. See asm_fpmath. */ 294 XO_ROUNDSD = 0x0b3a0ffc, /* Really 66 0f 3a 0b. See asm_fpmath. */
278 XO_UCOMISD = XO_660f(2e), 295 XO_UCOMISD = XO_660f(2e),
279 XO_CVTSI2SD = XO_f20f(2a), 296 XO_CVTSI2SD = XO_f20f(2a),
280 XO_CVTSD2SI = XO_f20f(2d),
281 XO_CVTTSD2SI= XO_f20f(2c), 297 XO_CVTTSD2SI= XO_f20f(2c),
282 XO_CVTSI2SS = XO_f30f(2a), 298 XO_CVTSI2SS = XO_f30f(2a),
283 XO_CVTSS2SI = XO_f30f(2d),
284 XO_CVTTSS2SI= XO_f30f(2c), 299 XO_CVTTSS2SI= XO_f30f(2c),
285 XO_CVTSS2SD = XO_f30f(5a), 300 XO_CVTSS2SD = XO_f30f(5a),
286 XO_CVTSD2SS = XO_f20f(5a), 301 XO_CVTSD2SS = XO_f20f(5a),