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* Merge branch 'master' into v2.1Mike Pall2016-03-031-1/+1
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| * Bump copyright date to 2016.Mike Pall2016-03-031-1/+1
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* | Merge branch 'master' into v2.1Mike Pall2016-02-101-1/+1
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| * Don't allocate unused 2nd result register in JIT compiler backend.Mike Pall2016-02-101-1/+1
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* | Generalize LJ_SOFTFP dependencies in lj_asm.c.Mike Pall2016-02-091-11/+1
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* | Merge branch 'master' into v2.1Mike Pall2015-01-061-1/+1
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| * Bump copyright date to 2015.Mike Pall2015-01-051-1/+1
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* | Add LJ_FR2 mode: Two-slot frame info.Mike Pall2015-01-031-1/+1
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* | Merge branch 'master' into v2.1Mike Pall2014-02-201-2/+5
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| * Prevent BASE register coalescing if parent uses IR_RETF.Mike Pall2014-02-191-2/+5
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* | Merge branch 'master' into v2.1Mike Pall2014-01-161-1/+1
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| * Bump copyright date to 2014.Mike Pall2014-01-161-1/+1
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* | Low-overhead profiler, part 4: JIT compiler support.Mike Pall2013-09-081-0/+10
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* | Save currently executing lua_State in g->cur_L.Mike Pall2013-08-301-4/+4
| | | | | | | | | | | | This is only a good approximation due to deficiencies in the design of the Lua/C API. It indicates _some_ valid state that is/was executing. Also reorder L->cframe stores to achieve a synchronously consistent state.
* | Merge branch 'master' into v2.1Mike Pall2013-07-311-7/+7
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| * ARM: Fix register allocation when rematerializing FPRs.Mike Pall2013-07-311-7/+7
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* | FFI: Compile VLA/VLS and large cdata allocs with default initialization.Mike Pall2013-05-241-10/+19
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* | Merge branch 'master' into v2.1Mike Pall2013-05-161-2/+2
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| * Handle calls with max. args in backends even after SPLIT.Mike Pall2013-05-161-2/+2
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* | Refactor CCallInfo representation for split arguments.Mike Pall2013-05-131-2/+2
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* | Combine IR instruction dispatch for all assembler backends.Mike Pall2013-04-221-185/+113
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* | Merge branch 'master' into v2.1Mike Pall2013-04-221-3/+8
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| * Fix compiler warning.Mike Pall2013-04-221-3/+8
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* | Reorganize generic operations common to all assembler backends.Mike Pall2013-04-221-99/+3
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* | Compile string concatenations (BC_CAT).Mike Pall2013-04-211-0/+5
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* ARM: Fix cache flush/sync for exit stubs of JIT-compiled code.Mike Pall2013-02-281-0/+1
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* Bump copyright date to 2013.Mike Pall2013-02-111-1/+1
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* ARM: Fix code generation for integer math.min/math.max.Mike Pall2012-12-021-2/+2
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* ARM: Fix armhf call argument handling.Mike Pall2012-12-021-1/+1
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* ARM: Drop hard-fp variants of floor/ceil/trunc.Mike Pall2012-10-151-8/+16
| | | | Soft-fp variants are faster on a Cortex-A9. Duh.
* ARM, MIPS: Fix workaround for argument GPRs vs. FPR remat.Mike Pall2012-10-151-1/+1
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* ARM, PPC, MIPS: Improve XLOAD operand fusion and register hinting.Mike Pall2012-08-271-1/+1
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* Replace strtod() with builtin string to number conversion.Mike Pall2012-08-251-1/+1
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* ARM: Fix base register coalescing.Mike Pall2012-08-251-3/+6
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* ARM: Fix commit ceaa60c0.Mike Pall2012-08-251-2/+5
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* ARM: Don't use argument GPRs to rematerialize FPR arguments.Mike Pall2012-08-191-4/+15
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* ARM: Fix calls to hard-float floor/ceil/trunc.Mike Pall2012-08-191-1/+2
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* ARM: Add VFP and hard-float ABI variants to JIT compiler.Mike Pall2012-08-091-105/+630
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* FFI: Box all accessed or returned enums.Mike Pall2012-07-171-1/+1
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* Remove unneeded snapshot preps for sunk stores.Mike Pall2012-07-031-13/+5
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* Avoid pesky compiler warnings about C++ keywords (eh?).Mike Pall2012-07-031-6/+6
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* Add allocation sinking and store sinking optimization.Mike Pall2012-07-021-18/+31
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* Add explicit IR_GCSTEP instruction.Mike Pall2012-07-021-1/+2
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* Use HIOP for XSTORE in SPLIT pass.Mike Pall2012-07-021-17/+27
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* ARM: Fix conditional branch fixup for OBAR.Mike Pall2012-04-261-2/+2
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* ARM: Fix register allocation for ldrd-optimized HREFK.Mike Pall2012-04-261-1/+2
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* ARM: Reorder type/value tests to silence Valgrind.Mike Pall2012-04-261-5/+4
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* Bump copyright date to 2012.Mike Pall2012-01-231-1/+1
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* Move helper for syncing data/instruction cache to lj_mcode.c.Mike Pall2011-12-121-1/+1
| | | | Sync caches after dynamic code generation for FFI callbacks.
* ARM: Fix stack check for spilled BASE in parent.Mike Pall2011-12-101-7/+5
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