From 496d3753f559b5bea5a1d48d48c9193608251a74 Mon Sep 17 00:00:00 2001
From: Mike Pall <mike>
Date: Tue, 31 May 2011 21:38:16 +0200
Subject: ARM: Optimize hash algorithm for 3-operand CPUs.
---
src/lj_tab.h | 8 ++++++++
1 file changed, 8 insertions(+)
(limited to 'src')
diff --git a/src/lj_tab.h b/src/lj_tab.h
index 0ccfb9b4..76e96f13 100644
--- a/src/lj_tab.h
+++ b/src/lj_tab.h
@@ -17,9 +17,17 @@
/* Scramble the bits of numbers and pointers. */
static LJ_AINLINE uint32_t hashrot(uint32_t lo, uint32_t hi)
{
+#if LJ_TARGET_X86ORX64
+ /* Prefer variant that compiles well for a 2-operand CPU. */
lo ^= hi; hi = lj_rol(hi, HASH_ROT1);
lo -= hi; hi = lj_rol(hi, HASH_ROT2);
hi ^= lo; hi -= lj_rol(lo, HASH_ROT3);
+#else
+ lo ^= hi;
+ lo = lo - lj_rol(hi, HASH_ROT1);
+ hi = lo ^ lj_rol(hi, HASH_ROT1 + HASH_ROT2);
+ hi = hi - lj_rol(lo, HASH_ROT3);
+#endif
return hi;
}
--
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