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authorcvs2svn <admin@example.com>2025-04-14 17:32:06 +0000
committercvs2svn <admin@example.com>2025-04-14 17:32:06 +0000
commiteb8dd9dca1228af0cd132f515509051ecfabf6f6 (patch)
treeedb6da6af7e865d488dc1a29309f1e1ec226e603 /src/lib/libcrypto/rc4/asm/rc4-586.pl
parent247f0352e0ed72a4f476db9dc91f4d982bc83eb2 (diff)
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1#!/usr/bin/env perl
2
3# ====================================================================
4# [Re]written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
5# project. The module is, however, dual licensed under OpenSSL and
6# CRYPTOGAMS licenses depending on where you obtain it. For further
7# details see http://www.openssl.org/~appro/cryptogams/.
8# ====================================================================
9
10# At some point it became apparent that the original SSLeay RC4
11# assembler implementation performs suboptimally on latest IA-32
12# microarchitectures. After re-tuning performance has changed as
13# following:
14#
15# Pentium -10%
16# Pentium III +12%
17# AMD +50%(*)
18# P4 +250%(**)
19#
20# (*) This number is actually a trade-off:-) It's possible to
21# achieve +72%, but at the cost of -48% off PIII performance.
22# In other words code performing further 13% faster on AMD
23# would perform almost 2 times slower on Intel PIII...
24# For reference! This code delivers ~80% of rc4-amd64.pl
25# performance on the same Opteron machine.
26# (**) This number requires compressed key schedule set up by
27# RC4_set_key [see commentary below for further details].
28#
29# <appro@fy.chalmers.se>
30
31# May 2011
32#
33# Optimize for Core2 and Westmere [and incidentally Opteron]. Current
34# performance in cycles per processed byte (less is better) and
35# improvement relative to previous version of this module is:
36#
37# Pentium 10.2 # original numbers
38# Pentium III 7.8(*)
39# Intel P4 7.5
40#
41# Opteron 6.1/+20% # new MMX numbers
42# Core2 5.3/+67%(**)
43# Westmere 5.1/+94%(**)
44# Sandy Bridge 5.0/+8%
45# Atom 12.6/+6%
46#
47# (*) PIII can actually deliver 6.6 cycles per byte with MMX code,
48# but this specific code performs poorly on Core2. And vice
49# versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs
50# poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU
51# [anymore], I chose to discard PIII-specific code path and opt
52# for original IALU-only code, which is why MMX/SSE code path
53# is guarded by SSE2 bit (see below), not MMX/SSE.
54# (**) Performance vs. block size on Core2 and Westmere had a maximum
55# at ... 64 bytes block size. And it was quite a maximum, 40-60%
56# in comparison to largest 8KB block size. Above improvement
57# coefficients are for the largest block size.
58
59$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
60push(@INC,"${dir}","${dir}../../perlasm");
61require "x86asm.pl";
62
63&asm_init($ARGV[0],"rc4-586.pl");
64
65$xx="eax";
66$yy="ebx";
67$tx="ecx";
68$ty="edx";
69$inp="esi";
70$out="ebp";
71$dat="edi";
72
73sub RC4_loop {
74 my $i=shift;
75 my $func = ($i==0)?*mov:*or;
76
77 &add (&LB($yy),&LB($tx));
78 &mov ($ty,&DWP(0,$dat,$yy,4));
79 &mov (&DWP(0,$dat,$yy,4),$tx);
80 &mov (&DWP(0,$dat,$xx,4),$ty);
81 &add ($ty,$tx);
82 &inc (&LB($xx));
83 &and ($ty,0xff);
84 &ror ($out,8) if ($i!=0);
85 if ($i<3) {
86 &mov ($tx,&DWP(0,$dat,$xx,4));
87 } else {
88 &mov ($tx,&wparam(3)); # reload [re-biased] out
89 }
90 &$func ($out,&DWP(0,$dat,$ty,4));
91}
92
93if ($alt=0) {
94 # >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron,
95 # but ~40% slower on Core2 and Westmere... Attempt to add movz
96 # brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet
97 # on Core2 with movz it's almost 20% slower than below alternative
98 # code... Yes, it's a total mess...
99 my @XX=($xx,$out);
100 $RC4_loop_mmx = sub { # SSE actually...
101 my $i=shift;
102 my $j=$i<=0?0:$i>>1;
103 my $mm=$i<=0?"mm0":"mm".($i&1);
104
105 &add (&LB($yy),&LB($tx));
106 &lea (@XX[1],&DWP(1,@XX[0]));
107 &pxor ("mm2","mm0") if ($i==0);
108 &psllq ("mm1",8) if ($i==0);
109 &and (@XX[1],0xff);
110 &pxor ("mm0","mm0") if ($i<=0);
111 &mov ($ty,&DWP(0,$dat,$yy,4));
112 &mov (&DWP(0,$dat,$yy,4),$tx);
113 &pxor ("mm1","mm2") if ($i==0);
114 &mov (&DWP(0,$dat,$XX[0],4),$ty);
115 &add (&LB($ty),&LB($tx));
116 &movd (@XX[0],"mm7") if ($i==0);
117 &mov ($tx,&DWP(0,$dat,@XX[1],4));
118 &pxor ("mm1","mm1") if ($i==1);
119 &movq ("mm2",&QWP(0,$inp)) if ($i==1);
120 &movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0);
121 &pinsrw ($mm,&DWP(0,$dat,$ty,4),$j);
122
123 push (@XX,shift(@XX)) if ($i>=0);
124 }
125} else {
126 # Using pinsrw here improves performance on Intel CPUs by 2-3%, but
127 # brings down AMD by 7%...
128 $RC4_loop_mmx = sub {
129 my $i=shift;
130
131 &add (&LB($yy),&LB($tx));
132 &psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1);
133 &mov ($ty,&DWP(0,$dat,$yy,4));
134 &mov (&DWP(0,$dat,$yy,4),$tx);
135 &mov (&DWP(0,$dat,$xx,4),$ty);
136 &inc ($xx);
137 &add ($ty,$tx);
138 &movz ($xx,&LB($xx)); # (*)
139 &movz ($ty,&LB($ty)); # (*)
140 &pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0);
141 &movq ("mm0",&QWP(0,$inp)) if ($i<=0);
142 &movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0);
143 &mov ($tx,&DWP(0,$dat,$xx,4));
144 &movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4));
145
146 # (*) This is the key to Core2 and Westmere performance.
147 # Without movz out-of-order execution logic confuses
148 # itself and fails to reorder loads and stores. Problem
149 # appears to be fixed in Sandy Bridge...
150 }
151}
152
153&external_label("OPENSSL_ia32cap_P");
154
155# void rc4_internal(RC4_KEY *key, size_t len, const unsigned char *inp,
156# unsigned char *out);
157&function_begin("rc4_internal");
158 &mov ($dat,&wparam(0)); # load key schedule pointer
159 &mov ($ty, &wparam(1)); # load len
160 &mov ($inp,&wparam(2)); # load inp
161 &mov ($out,&wparam(3)); # load out
162
163 &xor ($xx,$xx); # avoid partial register stalls
164 &xor ($yy,$yy);
165
166 &cmp ($ty,0); # safety net
167 &je (&label("abort"));
168
169 &mov (&LB($xx),&BP(0,$dat)); # load key->x
170 &mov (&LB($yy),&BP(4,$dat)); # load key->y
171 &add ($dat,8);
172
173 &lea ($tx,&DWP(0,$inp,$ty));
174 &sub ($out,$inp); # re-bias out
175 &mov (&wparam(1),$tx); # save input+len
176
177 &inc (&LB($xx));
178
179 # detect compressed key schedule...
180 &cmp (&DWP(256,$dat),-1);
181 &je (&label("RC4_CHAR"));
182
183 &mov ($tx,&DWP(0,$dat,$xx,4));
184
185 &and ($ty,-4); # how many 4-byte chunks?
186 &jz (&label("loop1"));
187
188 &test ($ty,-8);
189 &mov (&wparam(3),$out); # $out as accumulator in these loops
190 &jz (&label("go4loop4"));
191
192 &picsetup($out);
193 &picsymbol($out, "OPENSSL_ia32cap_P", $out);
194 # check SSE2 bit [could have been MMX]
195 &bt (&DWP(0,$out),"\$IA32CAP_BIT0_SSE2");
196 &jnc (&label("go4loop4"));
197
198 &mov ($out,&wparam(3)) if (!$alt);
199 &movd ("mm7",&wparam(3)) if ($alt);
200 &and ($ty,-8);
201 &lea ($ty,&DWP(-8,$inp,$ty));
202 &mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8
203
204 &$RC4_loop_mmx(-1);
205 &jmp(&label("loop_mmx_enter"));
206
207 &set_label("loop_mmx",16);
208 &$RC4_loop_mmx(0);
209 &set_label("loop_mmx_enter");
210 for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); }
211 &mov ($ty,$yy);
212 &xor ($yy,$yy); # this is second key to Core2
213 &mov (&LB($yy),&LB($ty)); # and Westmere performance...
214 &cmp ($inp,&DWP(-4,$dat));
215 &lea ($inp,&DWP(8,$inp));
216 &jb (&label("loop_mmx"));
217
218 if ($alt) {
219 &movd ($out,"mm7");
220 &pxor ("mm2","mm0");
221 &psllq ("mm1",8);
222 &pxor ("mm1","mm2");
223 &movq (&QWP(-8,$out,$inp),"mm1");
224 } else {
225 &psllq ("mm1",56);
226 &pxor ("mm2","mm1");
227 &movq (&QWP(-8,$out,$inp),"mm2");
228 }
229 &emms ();
230
231 &cmp ($inp,&wparam(1)); # compare to input+len
232 &je (&label("done"));
233 &jmp (&label("loop1"));
234
235&set_label("go4loop4",16);
236 &lea ($ty,&DWP(-4,$inp,$ty));
237 &mov (&wparam(2),$ty); # save input+(len/4)*4-4
238
239 &set_label("loop4");
240 for ($i=0;$i<4;$i++) { RC4_loop($i); }
241 &ror ($out,8);
242 &xor ($out,&DWP(0,$inp));
243 &cmp ($inp,&wparam(2)); # compare to input+(len/4)*4-4
244 &mov (&DWP(0,$tx,$inp),$out);# $tx holds re-biased out here
245 &lea ($inp,&DWP(4,$inp));
246 &mov ($tx,&DWP(0,$dat,$xx,4));
247 &jb (&label("loop4"));
248
249 &cmp ($inp,&wparam(1)); # compare to input+len
250 &je (&label("done"));
251 &mov ($out,&wparam(3)); # restore $out
252
253 &set_label("loop1",16);
254 &add (&LB($yy),&LB($tx));
255 &mov ($ty,&DWP(0,$dat,$yy,4));
256 &mov (&DWP(0,$dat,$yy,4),$tx);
257 &mov (&DWP(0,$dat,$xx,4),$ty);
258 &add ($ty,$tx);
259 &inc (&LB($xx));
260 &and ($ty,0xff);
261 &mov ($ty,&DWP(0,$dat,$ty,4));
262 &xor (&LB($ty),&BP(0,$inp));
263 &lea ($inp,&DWP(1,$inp));
264 &mov ($tx,&DWP(0,$dat,$xx,4));
265 &cmp ($inp,&wparam(1)); # compare to input+len
266 &mov (&BP(-1,$out,$inp),&LB($ty));
267 &jb (&label("loop1"));
268
269 &jmp (&label("done"));
270
271# this is essentially Intel P4 specific codepath...
272&set_label("RC4_CHAR",16);
273 &movz ($tx,&BP(0,$dat,$xx));
274 # strangely enough unrolled loop performs over 20% slower...
275 &set_label("cloop1");
276 &add (&LB($yy),&LB($tx));
277 &movz ($ty,&BP(0,$dat,$yy));
278 &mov (&BP(0,$dat,$yy),&LB($tx));
279 &mov (&BP(0,$dat,$xx),&LB($ty));
280 &add (&LB($ty),&LB($tx));
281 &movz ($ty,&BP(0,$dat,$ty));
282 &add (&LB($xx),1);
283 &xor (&LB($ty),&BP(0,$inp));
284 &lea ($inp,&DWP(1,$inp));
285 &movz ($tx,&BP(0,$dat,$xx));
286 &cmp ($inp,&wparam(1));
287 &mov (&BP(-1,$out,$inp),&LB($ty));
288 &jb (&label("cloop1"));
289
290&set_label("done");
291 &dec (&LB($xx));
292 &mov (&DWP(-4,$dat),$yy); # save key->y
293 &mov (&BP(-8,$dat),&LB($xx)); # save key->x
294&set_label("abort");
295&function_end("rc4_internal");
296
297########################################################################
298
299$inp="esi";
300$out="edi";
301$idi="ebp";
302$ido="ecx";
303$idx="edx";
304
305# void rc4_set_key_internal(RC4_KEY *key,int len,const unsigned char *data);
306&function_begin("rc4_set_key_internal");
307 &mov ($out,&wparam(0)); # load key
308 &mov ($idi,&wparam(1)); # load len
309 &mov ($inp,&wparam(2)); # load data
310
311 &picsetup($idx);
312 &picsymbol($idx, "OPENSSL_ia32cap_P", $idx);
313
314 &lea ($out,&DWP(2*4,$out)); # &key->data
315 &lea ($inp,&DWP(0,$inp,$idi)); # $inp to point at the end
316 &neg ($idi);
317 &xor ("eax","eax");
318 &mov (&DWP(-4,$out),$idi); # borrow key->y
319
320 &bt (&DWP(0,$idx),"\$IA32CAP_BIT0_INTELP4");
321 &jc (&label("c1stloop"));
322
323&set_label("w1stloop",16);
324 &mov (&DWP(0,$out,"eax",4),"eax"); # key->data[i]=i;
325 &add (&LB("eax"),1); # i++;
326 &jnc (&label("w1stloop"));
327
328 &xor ($ido,$ido);
329 &xor ($idx,$idx);
330
331&set_label("w2ndloop",16);
332 &mov ("eax",&DWP(0,$out,$ido,4));
333 &add (&LB($idx),&BP(0,$inp,$idi));
334 &add (&LB($idx),&LB("eax"));
335 &add ($idi,1);
336 &mov ("ebx",&DWP(0,$out,$idx,4));
337 &jnz (&label("wnowrap"));
338 &mov ($idi,&DWP(-4,$out));
339 &set_label("wnowrap");
340 &mov (&DWP(0,$out,$idx,4),"eax");
341 &mov (&DWP(0,$out,$ido,4),"ebx");
342 &add (&LB($ido),1);
343 &jnc (&label("w2ndloop"));
344&jmp (&label("exit"));
345
346# Unlike all other x86 [and x86_64] implementations, Intel P4 core
347# [including EM64T] was found to perform poorly with above "32-bit" key
348# schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded
349# assembler turned out to be 3.5x if re-coded for compressed 8-bit one,
350# a.k.a. RC4_CHAR! It's however inappropriate to just switch to 8-bit
351# schedule for x86[_64], because non-P4 implementations suffer from
352# significant performance losses then, e.g. PIII exhibits >2x
353# deterioration, and so does Opteron. In order to assure optimal
354# all-round performance, we detect P4 at run-time and set up compressed
355# key schedule, which is recognized by RC4 procedure.
356
357&set_label("c1stloop",16);
358 &mov (&BP(0,$out,"eax"),&LB("eax")); # key->data[i]=i;
359 &add (&LB("eax"),1); # i++;
360 &jnc (&label("c1stloop"));
361
362 &xor ($ido,$ido);
363 &xor ($idx,$idx);
364 &xor ("ebx","ebx");
365
366&set_label("c2ndloop",16);
367 &mov (&LB("eax"),&BP(0,$out,$ido));
368 &add (&LB($idx),&BP(0,$inp,$idi));
369 &add (&LB($idx),&LB("eax"));
370 &add ($idi,1);
371 &mov (&LB("ebx"),&BP(0,$out,$idx));
372 &jnz (&label("cnowrap"));
373 &mov ($idi,&DWP(-4,$out));
374 &set_label("cnowrap");
375 &mov (&BP(0,$out,$idx),&LB("eax"));
376 &mov (&BP(0,$out,$ido),&LB("ebx"));
377 &add (&LB($ido),1);
378 &jnc (&label("c2ndloop"));
379
380 &mov (&DWP(256,$out),-1); # mark schedule as compressed
381
382&set_label("exit");
383 &xor ("eax","eax");
384 &mov (&DWP(-8,$out),"eax"); # key->x=0;
385 &mov (&DWP(-4,$out),"eax"); # key->y=0;
386&function_end("rc4_set_key_internal");
387
388&asm_finish();
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