Replace all uses of magic numbers when operating on OPENSSL_ia32_P[] by

meaningful constants in a private header file, so that reviewers can actually
get a chance to figure out what the code is attempting to do without knowing
all cpuid bits.

While there, turn it from an array of two 32-bit ints into a properly aligned
64-bit int.

Use of OPENSSL_ia32_P is now restricted to the assembler parts. C code will
now always use OPENSSL_cpu_caps() and check for the proper bits in the
whole 64-bit word it returns.

i386 tests and ok jsing@

3 files changed, 11 insertions, 10 deletions

diff --git a/src/lib/libcrypto/sha/asm/sha1-586.pl b/src/lib/libcrypto/sha/asm/sha1-586.pl
index 6fbea34d78..d29ed84706 100644
--- a/src/lib/libcrypto/sha/asm/sha1-586.pl
+++ b/src/lib/libcrypto/sha/asm/sha1-586.pl
@@ -303,15 +303,15 @@ if ($xmm) {
 
         &mov    ($A,&DWP(0,$T));
         &mov    ($D,&DWP(4,$T));
-        &test   ($D,1<<9);              # check SSSE3 bit
+        &test   ($D,"\$IA32CAP_MASK1_SSSE3");   # check SSSE3 bit
         &jz     (&label("x86"));
-        &test   ($A,1<<24);             # check FXSR bit
+        &test   ($A,"\$IA32CAP_MASK0_FXSR");    # check FXSR bit
         &jz     (&label("x86"));
         if ($ymm) {
-                &and    ($D,1<<28);             # mask AVX bit
-                &and    ($A,1<<30);             # mask "Intel CPU" bit
+                &and    ($D,"\$IA32CAP_MASK1_AVX");     # mask AVX bit
+                &and    ($A,"\$IA32CAP_MASK0_INTEL");   # mask "Intel CPU" bit
                 &or     ($A,$D);
-                &cmp    ($A,1<<28|1<<30);
+                &cmp    ($A,"\$(IA32CAP_MASK1_AVX | IA32CAP_MASK0_INTEL)");
                 &je     (&label("avx_shortcut"));
         }
         &jmp    (&label("ssse3_shortcut"));
diff --git a/src/lib/libcrypto/sha/asm/sha1-x86_64.pl b/src/lib/libcrypto/sha/asm/sha1-x86_64.pl
index f15c7ec39b..147d21570b 100755
--- a/src/lib/libcrypto/sha/asm/sha1-x86_64.pl
+++ b/src/lib/libcrypto/sha/asm/sha1-x86_64.pl
@@ -216,6 +216,7 @@ unshift(@xi,pop(@xi));
 $code.=<<___;
 .text
 .extern OPENSSL_ia32cap_P
+.hidden OPENSSL_ia32cap_P
 
 .globl  sha1_block_data_order
 .type   sha1_block_data_order,\@function,3
@@ -223,14 +224,14 @@ $code.=<<___;
 sha1_block_data_order:
         mov     OPENSSL_ia32cap_P+0(%rip),%r9d
         mov     OPENSSL_ia32cap_P+4(%rip),%r8d
-        test    \$`1<<9`,%r8d           # check SSSE3 bit
+        test    \$IA32CAP_MASK1_SSSE3,%r8d              # check SSSE3 bit
         jz      .Lialu
 ___
 $code.=<<___ if ($avx);
-        and     \$`1<<28`,%r8d          # mask AVX bit
-        and     \$`1<<30`,%r9d          # mask "Intel CPU" bit
+        and     \$IA32CAP_MASK1_AVX,%r8d                # mask AVX bit
+        and     \$IA32CAP_MASK0_INTEL,%r9d              # mask "Intel CPU" bit
         or      %r9d,%r8d
-        cmp     \$`1<<28|1<<30`,%r8d
+        cmp     \$(IA32CAP_MASK0_INTEL | IA32CAP_MASK1_AVX),%r8d
         je      _avx_shortcut
 ___
 $code.=<<___;
diff --git a/src/lib/libcrypto/sha/asm/sha512-586.pl b/src/lib/libcrypto/sha/asm/sha512-586.pl
index 7eab6a5b88..163361ebe9 100644
--- a/src/lib/libcrypto/sha/asm/sha512-586.pl
+++ b/src/lib/libcrypto/sha/asm/sha512-586.pl
@@ -284,7 +284,7 @@ sub BODY_00_15_x86 {
 
 if ($sse2) {
         &picmeup("edx","OPENSSL_ia32cap_P",$K512,&label("K512"));
-        &bt     (&DWP(0,"edx"),26);
+        &bt     (&DWP(0,"edx"),"\$IA32CAP_BIT0_SSE2");
         &jnc    (&label("loop_x86"));
 
         # load ctx->h[0-7]