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Diffstat (limited to 'src/lib/libcrypto/x86cpuid.pl')
-rw-r--r--src/lib/libcrypto/x86cpuid.pl192
1 files changed, 0 insertions, 192 deletions
diff --git a/src/lib/libcrypto/x86cpuid.pl b/src/lib/libcrypto/x86cpuid.pl
deleted file mode 100644
index 8a96cda6e6..0000000000
--- a/src/lib/libcrypto/x86cpuid.pl
+++ /dev/null
@@ -1,192 +0,0 @@
1#!/usr/bin/env perl
2
3$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
4push(@INC, "${dir}perlasm", "perlasm");
5require "x86asm.pl";
6
7&asm_init($ARGV[0],"x86cpuid");
8
9for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
10
11&function_begin("OPENSSL_ia32_cpuid");
12 &xor ("edx","edx");
13 &pushf ();
14 &pop ("eax");
15 &mov ("ecx","eax");
16 &xor ("eax",1<<21);
17 &push ("eax");
18 &popf ();
19 &pushf ();
20 &pop ("eax");
21 &xor ("ecx","eax");
22 &xor ("eax","eax");
23 &bt ("ecx",21);
24 &jnc (&label("nocpuid"));
25 &cpuid ();
26 &mov ("edi","eax"); # max value for standard query level
27
28 &xor ("eax","eax");
29 &cmp ("ebx",0x756e6547); # "Genu"
30 &setne (&LB("eax"));
31 &mov ("ebp","eax");
32 &cmp ("edx",0x49656e69); # "ineI"
33 &setne (&LB("eax"));
34 &or ("ebp","eax");
35 &cmp ("ecx",0x6c65746e); # "ntel"
36 &setne (&LB("eax"));
37 &or ("ebp","eax"); # 0 indicates Intel CPU
38 &jz (&label("intel"));
39
40 &cmp ("ebx",0x68747541); # "Auth"
41 &setne (&LB("eax"));
42 &mov ("esi","eax");
43 &cmp ("edx",0x69746E65); # "enti"
44 &setne (&LB("eax"));
45 &or ("esi","eax");
46 &cmp ("ecx",0x444D4163); # "cAMD"
47 &setne (&LB("eax"));
48 &or ("esi","eax"); # 0 indicates AMD CPU
49 &jnz (&label("intel"));
50
51 # AMD specific
52 &mov ("eax",0x80000000);
53 &cpuid ();
54 &cmp ("eax",0x80000001);
55 &jb (&label("intel"));
56 &mov ("esi","eax");
57 &mov ("eax",0x80000001);
58 &cpuid ();
59 &or ("ebp","ecx");
60 &and ("ebp",1<<11|1); # isolate XOP bit
61 &cmp ("esi",0x80000008);
62 &jb (&label("intel"));
63
64 &mov ("eax",0x80000008);
65 &cpuid ();
66 &movz ("esi",&LB("ecx")); # number of cores - 1
67 &inc ("esi"); # number of cores
68
69 &mov ("eax",1);
70 &xor ("ecx","ecx");
71 &cpuid ();
72 &bt ("edx",28);
73 &jnc (&label("generic"));
74 &shr ("ebx",16);
75 &and ("ebx",0xff);
76 &cmp ("ebx","esi");
77 &ja (&label("generic"));
78 &and ("edx",0xefffffff); # clear hyper-threading bit
79 &jmp (&label("generic"));
80
81&set_label("intel");
82 &cmp ("edi",4);
83 &mov ("edi",-1);
84 &jb (&label("nocacheinfo"));
85
86 &mov ("eax",4);
87 &mov ("ecx",0); # query L1D
88 &cpuid ();
89 &mov ("edi","eax");
90 &shr ("edi",14);
91 &and ("edi",0xfff); # number of cores -1 per L1D
92
93&set_label("nocacheinfo");
94 &mov ("eax",1);
95 &xor ("ecx","ecx");
96 &cpuid ();
97 &and ("edx",0xbfefffff); # force reserved bits #20, #30 to 0
98 &cmp ("ebp",0);
99 &jne (&label("notintel"));
100 &or ("edx",1<<30); # set reserved bit#30 on Intel CPUs
101 &and (&HB("eax"),15); # familiy ID
102 &cmp (&HB("eax"),15); # P4?
103 &jne (&label("notintel"));
104 &or ("edx",1<<20); # set reserved bit#20 to engage RC4_CHAR
105&set_label("notintel");
106 &bt ("edx",28); # test hyper-threading bit
107 &jnc (&label("generic"));
108 &and ("edx",0xefffffff);
109 &cmp ("edi",0);
110 &je (&label("generic"));
111
112 &or ("edx",0x10000000);
113 &shr ("ebx",16);
114 &cmp (&LB("ebx"),1);
115 &ja (&label("generic"));
116 &and ("edx",0xefffffff); # clear hyper-threading bit if not
117
118&set_label("generic");
119 &and ("ebp",1<<11); # isolate AMD XOP flag
120 &and ("ecx",0xfffff7ff); # force 11th bit to 0
121 &mov ("esi","edx");
122 &or ("ebp","ecx"); # merge AMD XOP flag
123
124 &bt ("ecx",27); # check OSXSAVE bit
125 &jnc (&label("clear_avx"));
126 &xor ("ecx","ecx");
127 &data_byte(0x0f,0x01,0xd0); # xgetbv
128 &and ("eax",6);
129 &cmp ("eax",6);
130 &je (&label("done"));
131 &cmp ("eax",2);
132 &je (&label("clear_avx"));
133&set_label("clear_xmm");
134 &and ("ebp",0xfdfffffd); # clear AESNI and PCLMULQDQ bits
135 &and ("esi",0xfeffffff); # clear FXSR
136&set_label("clear_avx");
137 &and ("ebp",0xefffe7ff); # clear AVX, FMA and AMD XOP bits
138&set_label("done");
139 &mov ("eax","esi");
140 &mov ("edx","ebp");
141&set_label("nocpuid");
142&function_end("OPENSSL_ia32_cpuid");
143
144&external_label("OPENSSL_ia32cap_P");
145
146&function_begin_B("OPENSSL_wipe_cpu","EXTRN\t_OPENSSL_ia32cap_P:DWORD");
147 &xor ("eax","eax");
148 &xor ("edx","edx");
149 &picmeup("ecx","OPENSSL_ia32cap_P");
150 &mov ("ecx",&DWP(0,"ecx"));
151 &bt (&DWP(0,"ecx"),1);
152 &jnc (&label("no_x87"));
153 if ($sse2) {
154 &and ("ecx",1<<26|1<<24); # check SSE2 and FXSR bits
155 &cmp ("ecx",1<<26|1<<24);
156 &jne (&label("no_sse2"));
157 &pxor ("xmm0","xmm0");
158 &pxor ("xmm1","xmm1");
159 &pxor ("xmm2","xmm2");
160 &pxor ("xmm3","xmm3");
161 &pxor ("xmm4","xmm4");
162 &pxor ("xmm5","xmm5");
163 &pxor ("xmm6","xmm6");
164 &pxor ("xmm7","xmm7");
165 &set_label("no_sse2");
166 }
167 # just a bunch of fldz to zap the fp/mm bank followed by finit...
168 &data_word(0xeed9eed9,0xeed9eed9,0xeed9eed9,0xeed9eed9,0x90e3db9b);
169&set_label("no_x87");
170 &lea ("eax",&DWP(4,"esp"));
171 &ret ();
172&function_end_B("OPENSSL_wipe_cpu");
173
174&function_begin_B("OPENSSL_atomic_add");
175 &mov ("edx",&DWP(4,"esp")); # fetch the pointer, 1st arg
176 &mov ("ecx",&DWP(8,"esp")); # fetch the increment, 2nd arg
177 &push ("ebx");
178 &nop ();
179 &mov ("eax",&DWP(0,"edx"));
180&set_label("spin");
181 &lea ("ebx",&DWP(0,"eax","ecx"));
182 &nop ();
183 &data_word(0x1ab10ff0); # lock; cmpxchg %ebx,(%edx) # %eax is envolved and is always reloaded
184 &jne (&label("spin"));
185 &mov ("eax","ebx"); # OpenSSL expects the new value
186 &pop ("ebx");
187 &ret ();
188&function_end_B("OPENSSL_atomic_add");
189
190&initseg("OPENSSL_cpuid_setup");
191
192&asm_finish();
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