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author | Mike Pall <mike> | 2017-02-20 02:35:24 +0100 |
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committer | Mike Pall <mike> | 2017-02-20 02:35:24 +0100 |
commit | 892d370edd36ef748f3b6095a80f77798fac9bee (patch) | |
tree | 7484e3498dc31bc03b2fa39b1f5087dca54d0645 | |
parent | ee33a1f9b33577e23e5ec0aedd5ebe1baeef7f7c (diff) | |
download | luajit-892d370edd36ef748f3b6095a80f77798fac9bee.tar.gz luajit-892d370edd36ef748f3b6095a80f77798fac9bee.tar.bz2 luajit-892d370edd36ef748f3b6095a80f77798fac9bee.zip |
MIPS: Don't use RID_GP as a scratch register.
-rw-r--r-- | src/lj_target_mips.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/lj_target_mips.h b/src/lj_target_mips.h index 8b108304..bed174b8 100644 --- a/src/lj_target_mips.h +++ b/src/lj_target_mips.h | |||
@@ -28,6 +28,7 @@ enum { | |||
28 | RID_MAX, | 28 | RID_MAX, |
29 | RID_ZERO = RID_R0, | 29 | RID_ZERO = RID_R0, |
30 | RID_TMP = RID_RA, | 30 | RID_TMP = RID_RA, |
31 | RID_GP = RID_R28, | ||
31 | 32 | ||
32 | /* Calling conventions. */ | 33 | /* Calling conventions. */ |
33 | RID_RET = RID_R2, | 34 | RID_RET = RID_R2, |
@@ -62,10 +63,10 @@ enum { | |||
62 | 63 | ||
63 | /* -- Register sets ------------------------------------------------------- */ | 64 | /* -- Register sets ------------------------------------------------------- */ |
64 | 65 | ||
65 | /* Make use of all registers, except ZERO, TMP, SP, SYS1, SYS2 and JGL. */ | 66 | /* Make use of all registers, except ZERO, TMP, SP, SYS1, SYS2, JGL and GP. */ |
66 | #define RSET_FIXED \ | 67 | #define RSET_FIXED \ |
67 | (RID2RSET(RID_ZERO)|RID2RSET(RID_TMP)|RID2RSET(RID_SP)|\ | 68 | (RID2RSET(RID_ZERO)|RID2RSET(RID_TMP)|RID2RSET(RID_SP)|\ |
68 | RID2RSET(RID_SYS1)|RID2RSET(RID_SYS2)|RID2RSET(RID_JGL)) | 69 | RID2RSET(RID_SYS1)|RID2RSET(RID_SYS2)|RID2RSET(RID_JGL)|RID2RSET(RID_GP)) |
69 | #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED) | 70 | #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED) |
70 | #define RSET_FPR \ | 71 | #define RSET_FPR \ |
71 | (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\ | 72 | (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\ |
@@ -77,7 +78,7 @@ enum { | |||
77 | 78 | ||
78 | #define RSET_SCRATCH_GPR \ | 79 | #define RSET_SCRATCH_GPR \ |
79 | (RSET_RANGE(RID_R1, RID_R15+1)|\ | 80 | (RSET_RANGE(RID_R1, RID_R15+1)|\ |
80 | RID2RSET(RID_R24)|RID2RSET(RID_R25)|RID2RSET(RID_R28)) | 81 | RID2RSET(RID_R24)|RID2RSET(RID_R25)) |
81 | #define RSET_SCRATCH_FPR \ | 82 | #define RSET_SCRATCH_FPR \ |
82 | (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\ | 83 | (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\ |
83 | RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\ | 84 | RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\ |