Add IR_PVAL instruction for non-slot parent links.

3 files changed, 4 insertions, 1 deletions

diff --git a/src/lj_asm.c b/src/lj_asm.c
index dccc4eab..9bce9292 100644
--- a/src/lj_asm.c
+++ b/src/lj_asm.c
@@ -1287,7 +1287,7 @@ static void asm_head_side(ASMState *as)
     IRIns *ir = IR(i);
     RegSP rs;
     lua_assert((ir->o == IR_SLOAD && (ir->op2 & IRSLOAD_PARENT)) ||
-               (LJ_SOFTFP && ir->o == IR_HIOP));
+               (LJ_SOFTFP && ir->o == IR_HIOP) || ir->o == IR_PVAL);
     rs = as->parentmap[i - REF_FIRST];
     if (ra_hasreg(ir->r)) {
       rset_clear(allow, ir->r);
diff --git a/src/lj_ir.h b/src/lj_ir.h
index b10c65df..7e14066a 100644
--- a/src/lj_ir.h
+++ b/src/lj_ir.h
@@ -33,6 +33,7 @@
   /* Miscellaneous ops. */ \
   _(NOP,        N , ___, ___) \
   _(BASE,       N , lit, lit) \
+  _(PVAL,       N , lit, ___) \
   _(GCSTEP,     S , ___, ___) \
   _(HIOP,       S , ref, ref) \
   _(LOOP,       S , ___, ___) \
diff --git a/src/lj_snap.c b/src/lj_snap.c
index c04d622d..11d7ad0c 100644
--- a/src/lj_snap.c
+++ b/src/lj_snap.c
@@ -339,6 +339,8 @@ IRIns *lj_snap_regspmap(GCtrace *T, SnapNo snapno, IRIns *ir)
       }
     } else if (LJ_SOFTFP && ir->o == IR_HIOP) {
       ref++;
+    } else if (ir->o == IR_PVAL) {
+      ref = ir->op1 + REF_BIAS;
     } else {
       break;
     }