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| author | Mike Pall <mike> | 2011-09-05 20:23:20 +0200 |
|---|---|---|
| committer | Mike Pall <mike> | 2011-09-05 20:23:20 +0200 |
| commit | 1b949dc60a64676589c14baa46a4b56969df3cf6 (patch) | |
| tree | 9e0f8807e728865e984c908201532b3dfa2ad61b /src | |
| parent | ae3317b186f8782aa282a78e8a57c2130ddeb3f7 (diff) | |
| download | luajit-1b949dc60a64676589c14baa46a4b56969df3cf6.tar.gz luajit-1b949dc60a64676589c14baa46a4b56969df3cf6.tar.bz2 luajit-1b949dc60a64676589c14baa46a4b56969df3cf6.zip | |
Use some register allocator helpers for multiple architectures.
Diffstat (limited to 'src')
| -rw-r--r-- | src/lj_asm.c | 70 | ||||
| -rw-r--r-- | src/lj_asm_arm.h | 67 |
2 files changed, 70 insertions, 67 deletions
diff --git a/src/lj_asm.c b/src/lj_asm.c index 204d332e..b12b7466 100644 --- a/src/lj_asm.c +++ b/src/lj_asm.c | |||
| @@ -678,6 +678,76 @@ static void ra_left(ASMState *as, Reg dest, IRRef lref) | |||
| 678 | } | 678 | } |
| 679 | } | 679 | } |
| 680 | } | 680 | } |
| 681 | #else | ||
| 682 | /* Similar to ra_left, except we override any hints. */ | ||
| 683 | static void ra_leftov(ASMState *as, Reg dest, IRRef lref) | ||
| 684 | { | ||
| 685 | IRIns *ir = IR(lref); | ||
| 686 | Reg left = ir->r; | ||
| 687 | if (ra_noreg(left)) { | ||
| 688 | ra_sethint(ir->r, dest); /* Propagate register hint. */ | ||
| 689 | left = ra_allocref(as, lref, | ||
| 690 | (LJ_SOFTFP || dest < RID_MAX_GPR) ? RSET_GPR : RSET_FPR); | ||
| 691 | } | ||
| 692 | ra_noweak(as, left); | ||
| 693 | if (dest != left) { | ||
| 694 | /* Use register renaming if dest is the PHI reg. */ | ||
| 695 | if (irt_isphi(ir->t) && as->phireg[dest] == lref) { | ||
| 696 | ra_modified(as, left); | ||
| 697 | ra_rename(as, left, dest); | ||
| 698 | } else { | ||
| 699 | emit_movrr(as, ir, dest, left); | ||
| 700 | } | ||
| 701 | } | ||
| 702 | } | ||
| 703 | #endif | ||
| 704 | |||
| 705 | #if !LJ_TARGET_X86ORX64 | ||
| 706 | /* Force a RID_RET/RID_RETHI destination register pair (marked as free). */ | ||
| 707 | static void ra_destpair(ASMState *as, IRIns *ir) | ||
| 708 | { | ||
| 709 | Reg destlo = ir->r, desthi = (ir+1)->r; | ||
| 710 | /* First spill unrelated refs blocking the destination registers. */ | ||
| 711 | if (!rset_test(as->freeset, RID_RET) && | ||
| 712 | destlo != RID_RET && desthi != RID_RET) | ||
| 713 | ra_restore(as, regcost_ref(as->cost[RID_RET])); | ||
| 714 | if (!rset_test(as->freeset, RID_RETHI) && | ||
| 715 | destlo != RID_RETHI && desthi != RID_RETHI) | ||
| 716 | ra_restore(as, regcost_ref(as->cost[RID_RETHI])); | ||
| 717 | /* Next free the destination registers (if any). */ | ||
| 718 | if (ra_hasreg(destlo)) { | ||
| 719 | ra_free(as, destlo); | ||
| 720 | ra_modified(as, destlo); | ||
| 721 | } else { | ||
| 722 | destlo = RID_RET; | ||
| 723 | } | ||
| 724 | if (ra_hasreg(desthi)) { | ||
| 725 | ra_free(as, desthi); | ||
| 726 | ra_modified(as, desthi); | ||
| 727 | } else { | ||
| 728 | desthi = RID_RETHI; | ||
| 729 | } | ||
| 730 | /* Check for conflicts and shuffle the registers as needed. */ | ||
| 731 | if (destlo == RID_RETHI) { | ||
| 732 | if (desthi == RID_RET) { | ||
| 733 | emit_movrr(as, ir, RID_RETHI, RID_TMP); | ||
| 734 | emit_movrr(as, ir, RID_RET, RID_RETHI); | ||
| 735 | emit_movrr(as, ir, RID_TMP, RID_RET); | ||
| 736 | } else { | ||
| 737 | emit_movrr(as, ir, RID_RETHI, RID_RET); | ||
| 738 | if (desthi != RID_RETHI) emit_movrr(as, ir, desthi, RID_RETHI); | ||
| 739 | } | ||
| 740 | } else if (desthi == RID_RET) { | ||
| 741 | emit_movrr(as, ir, RID_RET, RID_RETHI); | ||
| 742 | if (destlo != RID_RET) emit_movrr(as, ir, destlo, RID_RET); | ||
| 743 | } else { | ||
| 744 | if (desthi != RID_RETHI) emit_movrr(as, ir, desthi, RID_RETHI); | ||
| 745 | if (destlo != RID_RET) emit_movrr(as, ir, destlo, RID_RET); | ||
| 746 | } | ||
| 747 | /* Restore spill slots (if any). */ | ||
| 748 | if (ra_hasspill((ir+1)->s)) ra_save(as, ir+1, RID_RETHI); | ||
| 749 | if (ra_hasspill(ir->s)) ra_save(as, ir, RID_RET); | ||
| 750 | } | ||
| 681 | #endif | 751 | #endif |
| 682 | 752 | ||
| 683 | /* -- Snapshot handling --------- ----------------------------------------- */ | 753 | /* -- Snapshot handling --------- ----------------------------------------- */ |
diff --git a/src/lj_asm_arm.h b/src/lj_asm_arm.h index 99f3055f..ea1a6aea 100644 --- a/src/lj_asm_arm.h +++ b/src/lj_asm_arm.h | |||
| @@ -18,27 +18,6 @@ static Reg ra_hintalloc(ASMState *as, IRRef ref, Reg hint, RegSet allow) | |||
| 18 | return r; | 18 | return r; |
| 19 | } | 19 | } |
| 20 | 20 | ||
| 21 | /* Similar to ra_left, except we override any hints. */ | ||
| 22 | static void ra_leftov(ASMState *as, Reg dest, IRRef lref) | ||
| 23 | { | ||
| 24 | IRIns *ir = IR(lref); | ||
| 25 | Reg left = ir->r; | ||
| 26 | if (ra_noreg(left)) { | ||
| 27 | ra_sethint(ir->r, dest); /* Propagate register hint. */ | ||
| 28 | left = ra_allocref(as, lref, RSET_GPR); | ||
| 29 | } | ||
| 30 | ra_noweak(as, left); | ||
| 31 | if (dest != left) { | ||
| 32 | /* Use register renaming if dest is the PHI reg. */ | ||
| 33 | if (irt_isphi(ir->t) && as->phireg[dest] == lref) { | ||
| 34 | ra_modified(as, left); | ||
| 35 | ra_rename(as, left, dest); | ||
| 36 | } else { | ||
| 37 | emit_movrr(as, ir, dest, left); | ||
| 38 | } | ||
| 39 | } | ||
| 40 | } | ||
| 41 | |||
| 42 | /* Allocate a scratch register pair. */ | 21 | /* Allocate a scratch register pair. */ |
| 43 | static Reg ra_scratchpair(ASMState *as, RegSet allow) | 22 | static Reg ra_scratchpair(ASMState *as, RegSet allow) |
| 44 | { | 23 | { |
| @@ -69,52 +48,6 @@ static Reg ra_scratchpair(ASMState *as, RegSet allow) | |||
| 69 | return r; | 48 | return r; |
| 70 | } | 49 | } |
| 71 | 50 | ||
| 72 | /* Force a RID_RET/RID_RETHI destination register pair (marked as free). */ | ||
| 73 | static void ra_destpair(ASMState *as, IRIns *ir) | ||
| 74 | { | ||
| 75 | Reg destlo = ir->r, desthi = (ir+1)->r; | ||
| 76 | /* First spill unrelated refs blocking the destination registers. */ | ||
| 77 | if (!rset_test(as->freeset, RID_RET) && | ||
| 78 | destlo != RID_RET && desthi != RID_RET) | ||
| 79 | ra_restore(as, regcost_ref(as->cost[RID_RET])); | ||
| 80 | if (!rset_test(as->freeset, RID_RETHI) && | ||
| 81 | destlo != RID_RETHI && desthi != RID_RETHI) | ||
| 82 | ra_restore(as, regcost_ref(as->cost[RID_RETHI])); | ||
| 83 | /* Next free the destination registers (if any). */ | ||
| 84 | if (ra_hasreg(destlo)) { | ||
| 85 | ra_free(as, destlo); | ||
| 86 | ra_modified(as, destlo); | ||
| 87 | } else { | ||
| 88 | destlo = RID_RET; | ||
| 89 | } | ||
| 90 | if (ra_hasreg(desthi)) { | ||
| 91 | ra_free(as, desthi); | ||
| 92 | ra_modified(as, desthi); | ||
| 93 | } else { | ||
| 94 | desthi = RID_RETHI; | ||
| 95 | } | ||
| 96 | /* Check for conflicts and shuffle the registers as needed. */ | ||
| 97 | if (destlo == RID_RETHI) { | ||
| 98 | if (desthi == RID_RET) { | ||
| 99 | emit_movrr(as, ir, RID_RETHI, RID_TMP); | ||
| 100 | emit_movrr(as, ir, RID_RET, RID_RETHI); | ||
| 101 | emit_movrr(as, ir, RID_TMP, RID_RET); | ||
| 102 | } else { | ||
| 103 | emit_movrr(as, ir, RID_RETHI, RID_RET); | ||
| 104 | if (desthi != RID_RETHI) emit_movrr(as, ir, desthi, RID_RETHI); | ||
| 105 | } | ||
| 106 | } else if (desthi == RID_RET) { | ||
| 107 | emit_movrr(as, ir, RID_RET, RID_RETHI); | ||
| 108 | if (destlo != RID_RET) emit_movrr(as, ir, destlo, RID_RET); | ||
| 109 | } else { | ||
| 110 | if (desthi != RID_RETHI) emit_movrr(as, ir, desthi, RID_RETHI); | ||
| 111 | if (destlo != RID_RET) emit_movrr(as, ir, destlo, RID_RET); | ||
| 112 | } | ||
| 113 | /* Restore spill slots (if any). */ | ||
| 114 | if (ra_hasspill((ir+1)->s)) ra_save(as, ir+1, RID_RETHI); | ||
| 115 | if (ra_hasspill(ir->s)) ra_save(as, ir, RID_RET); | ||
| 116 | } | ||
| 117 | |||
| 118 | /* -- Guard handling ------------------------------------------------------ */ | 51 | /* -- Guard handling ------------------------------------------------------ */ |
| 119 | 52 | ||
| 120 | /* Generate an exit stub group at the bottom of the reserved MCode memory. */ | 53 | /* Generate an exit stub group at the bottom of the reserved MCode memory. */ |
