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author | Mike Pall <mike> | 2010-12-23 00:55:31 +0100 |
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committer | Mike Pall <mike> | 2010-12-23 00:55:31 +0100 |
commit | 6082f93919200f1c6f774224ac01e32c0ebaa5ac (patch) | |
tree | 9bcc5447ad8bae736559d2213113fd9e11e483f5 /src | |
parent | c0ffe7d39409b403b8e24484bd4f5ef67afa4507 (diff) | |
download | luajit-6082f93919200f1c6f774224ac01e32c0ebaa5ac.tar.gz luajit-6082f93919200f1c6f774224ac01e32c0ebaa5ac.tar.bz2 luajit-6082f93919200f1c6f774224ac01e32c0ebaa5ac.zip |
Improve register allocation for loops with variable shifts.
Diffstat (limited to 'src')
-rw-r--r-- | src/lj_asm.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/lj_asm.c b/src/lj_asm.c index 84c37275..687363e1 100644 --- a/src/lj_asm.c +++ b/src/lj_asm.c | |||
@@ -3801,8 +3801,11 @@ static void asm_setup_regsp(ASMState *as, GCtrace *T) | |||
3801 | break; | 3801 | break; |
3802 | /* Non-constant shift counts need to be in RID_ECX. */ | 3802 | /* Non-constant shift counts need to be in RID_ECX. */ |
3803 | case IR_BSHL: case IR_BSHR: case IR_BSAR: case IR_BROL: case IR_BROR: | 3803 | case IR_BSHL: case IR_BSHR: case IR_BSAR: case IR_BROL: case IR_BROR: |
3804 | if (!irref_isk(ir->op2) && !ra_hashint(IR(ir->op2)->r)) | 3804 | if (!irref_isk(ir->op2) && !ra_hashint(IR(ir->op2)->r)) { |
3805 | IR(ir->op2)->r = REGSP_HINT(RID_ECX); | 3805 | IR(ir->op2)->r = REGSP_HINT(RID_ECX); |
3806 | if (inloop) | ||
3807 | rset_set(as->modset, RID_ECX); | ||
3808 | } | ||
3806 | break; | 3809 | break; |
3807 | /* Do not propagate hints across type conversions. */ | 3810 | /* Do not propagate hints across type conversions. */ |
3808 | case IR_TONUM: case IR_TOINT: case IR_TOBIT: | 3811 | case IR_TONUM: case IR_TOINT: case IR_TOBIT: |