ARM: Add instruction/call decode + dispatch macros.

author: Mike Pall <mike> 2011-03-29 02:26:09 +0200
committer: Mike Pall <mike> 2011-03-29 02:26:09 +0200
commit: 71f976b02e36e69731f85a1c2126af16b47b0395 (patch)
tree: 8d6eaa75f1d827bcefd6f65a91203ac5dc647015 /src
parent: 98e3c8a8ff03a9919cd4c21ce5a3d077821b28c2 (diff)
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1 files changed, 79 insertions, 0 deletions
diff --git a/src/buildvm_arm.dasc b/src/buildvm_arm.dasc
index 9d2efa67..5d5ea37b 100644
--- a/src/buildvm_arm.dasc
+++ b/src/buildvm_arm.dasc
@@ -84,6 +84,85 @@
 |
 |//-----------------------------------------------------------------------
 |
+|// Access to frame relative to BASE.
+|.define FRAME_FUNC,    #-8
+|.define FRAME_PC,      #-4
+|
+|.macro decode_RA8, dst, ins; and dst, MASKR8, ins, lsr #5; .endmacro
+|.macro decode_RB8, dst, ins; and dst, MASKR8, ins, lsr #21; .endmacro
+|.macro decode_RC8, dst, ins; and dst, MASKR8, ins, lsr #13; .endmacro
+|.macro decode_RD, dst, ins; lsr dst, ins, #16; .endmacro
+|
+|// Instruction fetch.
+|.macro ins_NEXT1
+|  ldrb OP, [PC]
+|.endmacro
+|.macro ins_NEXT2
+|   ldr INS, [PC], #4
+|.endmacro
+|// Instruction decode+dispatch.
+|.macro ins_NEXT3
+|  ldr OP, [DISPATCH, OP, lsl #2]
+|   decode_RA8 RA, INS
+|   decode_RD RC, INS
+|  bx OP
+|.endmacro
+|.macro ins_NEXT
+|  ins_NEXT1
+|  ins_NEXT2
+|  ins_NEXT3
+|.endmacro
+|
+|// Instruction footer.
+|.if 1
+|  // Replicated dispatch. Less unpredictable branches, but higher I-Cache use.
+|  .define ins_next, ins_NEXT
+|  .define ins_next_, ins_NEXT
+|  .define ins_next1, ins_NEXT1
+|  .define ins_next2, ins_NEXT2
+|  .define ins_next3, ins_NEXT3
+|.else
+|  // Common dispatch. Lower I-Cache use, only one (very) unpredictable branch.
+|  // Affects only certain kinds of benchmarks (and only with -j off).
+|  .macro ins_next
+|    b ->ins_next
+|  .endmacro
+|  .macro ins_next1
+|  .endmacro
+|  .macro ins_next2
+|  .endmacro
+|  .macro ins_next3
+|    b ->ins_next
+|  .endmacro
+|  .macro ins_next_
+|  ->ins_next:
+|    ins_NEXT
+|  .endmacro
+|.endif
+|
+|// Avoid register name substitution for field name.
+#define field_pc        pc
+|
+|// Call decode and dispatch.
+|.macro ins_callt
+|  // BASE = new base, CARG3 = LFUNC/CFUNC, RC = nargs*8, FRAME_PC(BASE) = PC
+|  ldr PC, LFUNC:CARG3->field_pc
+|  ldrb OP, [PC]
+|   ldr INS, [PC], #4
+|  ldr OP, [DISPATCH, OP, lsl #2]
+|   decode_RA8 RA, INS
+|   add RA, RA, BASE
+|  bx OP
+|.endmacro
+|
+|.macro ins_call
+|  // BASE = new base, CARG3 = LFUNC/CFUNC, RC = nargs*8, PC = caller PC
+|  str PC, [BASE, FRAME_PC]
+|  ins_callt
+|.endmacro
+|
+|//-----------------------------------------------------------------------
+|
 |// Assumes DISPATCH is relative to GL.
 #define DISPATCH_GL(field)      (GG_DISP2G + (int)offsetof(global_State, field))
 #define DISPATCH_J(field)       (GG_DISP2J + (int)offsetof(jit_State, field))
author	Mike Pall <mike>	2011-03-29 02:26:09 +0200
committer	Mike Pall <mike>	2011-03-29 02:26:09 +0200
commit	71f976b02e36e69731f85a1c2126af16b47b0395 (patch)
tree	8d6eaa75f1d827bcefd6f65a91203ac5dc647015 /src
parent	98e3c8a8ff03a9919cd4c21ce5a3d077821b28c2 (diff)
download	luajit-71f976b02e36e69731f85a1c2126af16b47b0395.tar.gz luajit-71f976b02e36e69731f85a1c2126af16b47b0395.tar.bz2 luajit-71f976b02e36e69731f85a1c2126af16b47b0395.zip

diff --git a/src/buildvm_arm.dasc b/src/buildvm_arm.dasc index 9d2efa67..5d5ea37b 100644 --- a/src/buildvm_arm.dasc +++ b/src/buildvm_arm.dasc
@@ -84,6 +84,85 @@
84	\|	84	\|
85	\|//-----------------------------------------------------------------------	85	\|//-----------------------------------------------------------------------
86	\|	86	\|
		87	\|// Access to frame relative to BASE.
		88	\|.define FRAME_FUNC, #-8
		89	\|.define FRAME_PC, #-4
		90	\|
		91	\|.macro decode_RA8, dst, ins; and dst, MASKR8, ins, lsr #5; .endmacro
		92	\|.macro decode_RB8, dst, ins; and dst, MASKR8, ins, lsr #21; .endmacro
		93	\|.macro decode_RC8, dst, ins; and dst, MASKR8, ins, lsr #13; .endmacro
		94	\|.macro decode_RD, dst, ins; lsr dst, ins, #16; .endmacro
		95	\|
		96	\|// Instruction fetch.
		97	\|.macro ins_NEXT1
		98	\| ldrb OP, [PC]
		99	\|.endmacro
		100	\|.macro ins_NEXT2
		101	\| ldr INS, [PC], #4
		102	\|.endmacro
		103	\|// Instruction decode+dispatch.
		104	\|.macro ins_NEXT3
		105	\| ldr OP, [DISPATCH, OP, lsl #2]
		106	\| decode_RA8 RA, INS
		107	\| decode_RD RC, INS
		108	\| bx OP
		109	\|.endmacro
		110	\|.macro ins_NEXT
		111	\| ins_NEXT1
		112	\| ins_NEXT2
		113	\| ins_NEXT3
		114	\|.endmacro
		115	\|
		116	\|// Instruction footer.
		117	\|.if 1
		118	\| // Replicated dispatch. Less unpredictable branches, but higher I-Cache use.
		119	\| .define ins_next, ins_NEXT
		120	\| .define ins_next_, ins_NEXT
		121	\| .define ins_next1, ins_NEXT1
		122	\| .define ins_next2, ins_NEXT2
		123	\| .define ins_next3, ins_NEXT3
		124	\|.else
		125	\| // Common dispatch. Lower I-Cache use, only one (very) unpredictable branch.
		126	\| // Affects only certain kinds of benchmarks (and only with -j off).
		127	\| .macro ins_next
		128	\| b ->ins_next
		129	\| .endmacro
		130	\| .macro ins_next1
		131	\| .endmacro
		132	\| .macro ins_next2
		133	\| .endmacro
		134	\| .macro ins_next3
		135	\| b ->ins_next
		136	\| .endmacro
		137	\| .macro ins_next_
		138	\| ->ins_next:
		139	\| ins_NEXT
		140	\| .endmacro
		141	\|.endif
		142	\|
		143	\|// Avoid register name substitution for field name.
		144	#define field_pc pc
		145	\|
		146	\|// Call decode and dispatch.
		147	\|.macro ins_callt
		148	\| // BASE = new base, CARG3 = LFUNC/CFUNC, RC = nargs*8, FRAME_PC(BASE) = PC
		149	\| ldr PC, LFUNC:CARG3->field_pc
		150	\| ldrb OP, [PC]
		151	\| ldr INS, [PC], #4
		152	\| ldr OP, [DISPATCH, OP, lsl #2]
		153	\| decode_RA8 RA, INS
		154	\| add RA, RA, BASE
		155	\| bx OP
		156	\|.endmacro
		157	\|
		158	\|.macro ins_call
		159	\| // BASE = new base, CARG3 = LFUNC/CFUNC, RC = nargs*8, PC = caller PC
		160	\| str PC, [BASE, FRAME_PC]
		161	\| ins_callt
		162	\|.endmacro
		163	\|
		164	\|//-----------------------------------------------------------------------
		165	\|
87	\|// Assumes DISPATCH is relative to GL.	166	\|// Assumes DISPATCH is relative to GL.
88	#define DISPATCH_GL(field) (GG_DISP2G + (int)offsetof(global_State, field))	167	#define DISPATCH_GL(field) (GG_DISP2G + (int)offsetof(global_State, field))
89	#define DISPATCH_J(field) (GG_DISP2J + (int)offsetof(jit_State, field))	168	#define DISPATCH_J(field) (GG_DISP2J + (int)offsetof(jit_State, field))