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authorMike Pall <mike>2012-07-04 21:16:06 +0200
committerMike Pall <mike>2012-07-04 21:16:06 +0200
commit7c056488d96434fc9996ba8b2b2a684f03472b62 (patch)
treeacb4d00bc52c4b31023b3e47bc7765d8f1f29391 /src
parentbd782cedd5079a49e30310837c899e98ce11c95c (diff)
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Drop range limit for sunk stores relative to sunk allocation.
Diffstat (limited to 'src')
-rw-r--r--src/jit/dump.lua2
-rw-r--r--src/lj_asm.c21
-rw-r--r--src/lj_opt_sink.c10
-rw-r--r--src/lj_snap.c29
4 files changed, 50 insertions, 12 deletions
diff --git a/src/jit/dump.lua b/src/jit/dump.lua
index 98933971..e5871b8d 100644
--- a/src/jit/dump.lua
+++ b/src/jit/dump.lua
@@ -378,7 +378,7 @@ local function ridsp_name(ridsp, ins)
378 if not disass then disass = require("jit.dis_"..jit.arch) end 378 if not disass then disass = require("jit.dis_"..jit.arch) end
379 local rid, slot = band(ridsp, 0xff), shr(ridsp, 8) 379 local rid, slot = band(ridsp, 0xff), shr(ridsp, 8)
380 if rid == 253 or rid == 254 then 380 if rid == 253 or rid == 254 then
381 return slot == 0 and " {sink" or format(" {%04d", ins-slot) 381 return (slot == 0 or slot == 255) and " {sink" or format(" {%04d", ins-slot)
382 end 382 end
383 if ridsp > 255 then return format("[%x]", slot*4) end 383 if ridsp > 255 then return format("[%x]", slot*4) end
384 if rid < 128 then return disass.regname(rid) end 384 if rid < 128 then return disass.regname(rid) end
diff --git a/src/lj_asm.c b/src/lj_asm.c
index 15685d85..6ea5bc93 100644
--- a/src/lj_asm.c
+++ b/src/lj_asm.c
@@ -778,6 +778,23 @@ static int asm_snap_canremat(ASMState *as)
778 return 0; 778 return 0;
779} 779}
780 780
781/* Check whether a sunk store corresponds to an allocation. */
782static int asm_sunk_store(ASMState *as, IRIns *ira, IRIns *irs)
783{
784 if (irs->s == 255) {
785 if (irs->o == IR_ASTORE || irs->o == IR_HSTORE ||
786 irs->o == IR_FSTORE || irs->o == IR_XSTORE) {
787 IRIns *irk = IR(irs->op1);
788 if (irk->o == IR_AREF || irk->o == IR_HREFK)
789 irk = IR(irk->op1);
790 return (IR(irk->op1) == ira);
791 }
792 return 0;
793 } else {
794 return (ira + irs->s == irs); /* Quick check. */
795 }
796}
797
781/* Allocate register or spill slot for a ref that escapes to a snapshot. */ 798/* Allocate register or spill slot for a ref that escapes to a snapshot. */
782static void asm_snap_alloc1(ASMState *as, IRRef ref) 799static void asm_snap_alloc1(ASMState *as, IRRef ref)
783{ 800{
@@ -795,8 +812,8 @@ static void asm_snap_alloc1(ASMState *as, IRRef ref)
795 else { /* Allocate stored values for TNEW, TDUP and CNEW. */ 812 else { /* Allocate stored values for TNEW, TDUP and CNEW. */
796 IRIns *irs; 813 IRIns *irs;
797 lua_assert(ir->o == IR_TNEW || ir->o == IR_TDUP || ir->o == IR_CNEW); 814 lua_assert(ir->o == IR_TNEW || ir->o == IR_TDUP || ir->o == IR_CNEW);
798 for (irs = IR(as->curins); irs > ir; irs--) 815 for (irs = IR(as->snapref-1); irs > ir; irs--)
799 if (irs->r == RID_SINK && ir + irs->s == irs) { 816 if (irs->r == RID_SINK && asm_sunk_store(as, ir, irs)) {
800 lua_assert(irs->o == IR_ASTORE || irs->o == IR_HSTORE || 817 lua_assert(irs->o == IR_ASTORE || irs->o == IR_HSTORE ||
801 irs->o == IR_FSTORE || irs->o == IR_XSTORE); 818 irs->o == IR_FSTORE || irs->o == IR_XSTORE);
802 asm_snap_alloc1(as, irs->op2); 819 asm_snap_alloc1(as, irs->op2);
diff --git a/src/lj_opt_sink.c b/src/lj_opt_sink.c
index 937cccc7..b7a3af2d 100644
--- a/src/lj_opt_sink.c
+++ b/src/lj_opt_sink.c
@@ -32,8 +32,6 @@ static IRIns *sink_checkalloc(jit_State *J, IRIns *irs)
32 ir = IR(ir->op1); 32 ir = IR(ir->op1);
33 if (!(ir->o == IR_TNEW || ir->o == IR_TDUP || ir->o == IR_CNEW)) 33 if (!(ir->o == IR_TNEW || ir->o == IR_TDUP || ir->o == IR_CNEW))
34 return NULL; /* Not an allocation. */ 34 return NULL; /* Not an allocation. */
35 if (ir + 255 < irs)
36 return NULL; /* Out of range. */
37 return ir; /* Return allocation. */ 35 return ir; /* Return allocation. */
38} 36}
39 37
@@ -173,10 +171,12 @@ static void sink_sweep_ins(jit_State *J)
173 switch (ir->o) { 171 switch (ir->o) {
174 case IR_ASTORE: case IR_HSTORE: case IR_FSTORE: case IR_XSTORE: { 172 case IR_ASTORE: case IR_HSTORE: case IR_FSTORE: case IR_XSTORE: {
175 IRIns *ira = sink_checkalloc(J, ir); 173 IRIns *ira = sink_checkalloc(J, ir);
176 if (ira && !irt_ismarked(ira->t)) 174 if (ira && !irt_ismarked(ira->t)) {
177 ir->prev = REGSP(RID_SINK, (int)(ir - ira)); 175 int delta = (int)(ir - ira);
178 else 176 ir->prev = REGSP(RID_SINK, delta > 255 ? 255 : delta);
177 } else {
179 ir->prev = REGSP_INIT; 178 ir->prev = REGSP_INIT;
179 }
180 break; 180 break;
181 } 181 }
182 case IR_NEWREF: 182 case IR_NEWREF:
diff --git a/src/lj_snap.c b/src/lj_snap.c
index 9fae57d8..b9a82008 100644
--- a/src/lj_snap.c
+++ b/src/lj_snap.c
@@ -403,6 +403,27 @@ static TRef snap_pref(jit_State *J, GCtrace *T, SnapEntry *map, MSize nmax,
403 return tr; 403 return tr;
404} 404}
405 405
406/* Check whether a sunk store corresponds to an allocation. Slow path. */
407static int snap_sunk_store2(jit_State *J, IRIns *ira, IRIns *irs)
408{
409 if (irs->o == IR_ASTORE || irs->o == IR_HSTORE ||
410 irs->o == IR_FSTORE || irs->o == IR_XSTORE) {
411 IRIns *irk = IR(irs->op1);
412 if (irk->o == IR_AREF || irk->o == IR_HREFK)
413 irk = IR(irk->op1);
414 return (IR(irk->op1) == ira);
415 }
416 return 0;
417}
418
419/* Check whether a sunk store corresponds to an allocation. Fast path. */
420static LJ_AINLINE int snap_sunk_store(jit_State *J, IRIns *ira, IRIns *irs)
421{
422 if (irs->s != 255)
423 return (ira + irs->s == irs); /* Fast check. */
424 return snap_sunk_store2(J, ira, irs);
425}
426
406/* Replay snapshot state to setup side trace. */ 427/* Replay snapshot state to setup side trace. */
407void lj_snap_replay(jit_State *J, GCtrace *T) 428void lj_snap_replay(jit_State *J, GCtrace *T)
408{ 429{
@@ -464,7 +485,7 @@ void lj_snap_replay(jit_State *J, GCtrace *T)
464 } else { 485 } else {
465 IRIns *irs; 486 IRIns *irs;
466 for (irs = ir+1; irs < irlast; irs++) 487 for (irs = ir+1; irs < irlast; irs++)
467 if (irs->r == RID_SINK && ir + irs->s == irs) { 488 if (irs->r == RID_SINK && snap_sunk_store(J, ir, irs)) {
468 if (snap_pref(J, T, map, nent, seen, irs->op2) == 0) 489 if (snap_pref(J, T, map, nent, seen, irs->op2) == 0)
469 snap_pref(J, T, map, nent, seen, T->ir[irs->op2].op1); 490 snap_pref(J, T, map, nent, seen, T->ir[irs->op2].op1);
470 else if ((LJ_SOFTFP || (LJ_32 && LJ_HASFFI)) && 491 else if ((LJ_SOFTFP || (LJ_32 && LJ_HASFFI)) &&
@@ -504,7 +525,7 @@ void lj_snap_replay(jit_State *J, GCtrace *T)
504 TRef tr = emitir(ir->ot, op1, op2); 525 TRef tr = emitir(ir->ot, op1, op2);
505 J->slot[snap_slot(sn)] = tr; 526 J->slot[snap_slot(sn)] = tr;
506 for (irs = ir+1; irs < irlast; irs++) 527 for (irs = ir+1; irs < irlast; irs++)
507 if (irs->r == RID_SINK && ir + irs->s == irs) { 528 if (irs->r == RID_SINK && snap_sunk_store(J, ir, irs)) {
508 IRIns *irr = &T->ir[irs->op1]; 529 IRIns *irr = &T->ir[irs->op1];
509 TRef val, key = irr->op2, tmp = tr; 530 TRef val, key = irr->op2, tmp = tr;
510 if (irr->o != IR_FREF) { 531 if (irr->o != IR_FREF) {
@@ -700,7 +721,7 @@ static void snap_unsink(jit_State *J, GCtrace *T, ExitState *ex,
700 } else { 721 } else {
701 IRIns *irs, *irlast = &T->ir[T->snap[snapno].ref]; 722 IRIns *irs, *irlast = &T->ir[T->snap[snapno].ref];
702 for (irs = ir+1; irs < irlast; irs++) 723 for (irs = ir+1; irs < irlast; irs++)
703 if (irs->r == RID_SINK && ir + irs->s == irs) { 724 if (irs->r == RID_SINK && snap_sunk_store(J, ir, irs)) {
704 IRIns *iro = &T->ir[T->ir[irs->op1].op2]; 725 IRIns *iro = &T->ir[T->ir[irs->op1].op2];
705 uint8_t *p = (uint8_t *)cd; 726 uint8_t *p = (uint8_t *)cd;
706 CTSize szs; 727 CTSize szs;
@@ -733,7 +754,7 @@ static void snap_unsink(jit_State *J, GCtrace *T, ExitState *ex,
733 settabV(J->L, o, t); 754 settabV(J->L, o, t);
734 irlast = &T->ir[T->snap[snapno].ref]; 755 irlast = &T->ir[T->snap[snapno].ref];
735 for (irs = ir+1; irs < irlast; irs++) 756 for (irs = ir+1; irs < irlast; irs++)
736 if (irs->r == RID_SINK && ir + irs->s == irs) { 757 if (irs->r == RID_SINK && snap_sunk_store(J, ir, irs)) {
737 IRIns *irk = &T->ir[irs->op1]; 758 IRIns *irk = &T->ir[irs->op1];
738 TValue tmp, *val; 759 TValue tmp, *val;
739 lua_assert(irs->o == IR_ASTORE || irs->o == IR_HSTORE || 760 lua_assert(irs->o == IR_ASTORE || irs->o == IR_HSTORE ||