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author | Mike Pall <mike> | 2011-05-09 22:39:53 +0200 |
---|---|---|
committer | Mike Pall <mike> | 2011-05-09 22:39:53 +0200 |
commit | c8308e2a87e36985bf169529c484d1eb8470c907 (patch) | |
tree | 04e58e350bb6bc4977fbb0d921c275cdf62d8413 /src | |
parent | 67d3ac9b19caba68069e83d1e3e9de14994d66cd (diff) | |
download | luajit-c8308e2a87e36985bf169529c484d1eb8470c907.tar.gz luajit-c8308e2a87e36985bf169529c484d1eb8470c907.tar.bz2 luajit-c8308e2a87e36985bf169529c484d1eb8470c907.zip |
ARM: Interpreter/JIT integration, part #1.
Diffstat (limited to 'src')
-rw-r--r-- | src/buildvm_arm.dasc | 74 |
1 files changed, 61 insertions, 13 deletions
diff --git a/src/buildvm_arm.dasc b/src/buildvm_arm.dasc index dadfc734..1cdfc54b 100644 --- a/src/buildvm_arm.dasc +++ b/src/buildvm_arm.dasc | |||
@@ -185,12 +185,23 @@ | |||
185 | | | 185 | | |
186 | #define PC2PROTO(field) ((int)offsetof(GCproto, field)-(int)sizeof(GCproto)) | 186 | #define PC2PROTO(field) ((int)offsetof(GCproto, field)-(int)sizeof(GCproto)) |
187 | | | 187 | | |
188 | |.macro hotcheck | ||
189 | | lsr CARG1, PC, #1 | ||
190 | | and CARG1, CARG1, #126 | ||
191 | | sub CARG1, CARG1, #-GG_DISP2HOT | ||
192 | | ldrh CARG2, [DISPATCH, CARG1] | ||
193 | | subs CARG2, CARG2, #1 | ||
194 | | strh CARG2, [DISPATCH, CARG1] | ||
195 | |.endmacro | ||
196 | | | ||
188 | |.macro hotloop | 197 | |.macro hotloop |
189 | | NYI | 198 | | hotcheck |
199 | | beq ->vm_hotloop | ||
190 | |.endmacro | 200 | |.endmacro |
191 | | | 201 | | |
192 | |.macro hotcall | 202 | |.macro hotcall |
193 | | NYI | 203 | | hotcheck |
204 | | beq ->vm_hotcall | ||
194 | |.endmacro | 205 | |.endmacro |
195 | | | 206 | | |
196 | |// Set current VM state. | 207 | |// Set current VM state. |
@@ -1811,7 +1822,17 @@ static void build_subroutines(BuildCtx *ctx) | |||
1811 | | | 1822 | | |
1812 | |->vm_record: // Dispatch target for recording phase. | 1823 | |->vm_record: // Dispatch target for recording phase. |
1813 | #if LJ_HASJIT | 1824 | #if LJ_HASJIT |
1814 | | NYI | 1825 | | ldrb CARG1, [DISPATCH, #DISPATCH_GL(hookmask)] |
1826 | | tst CARG1, #HOOK_VMEVENT // No recording while in vmevent. | ||
1827 | | bne >5 | ||
1828 | | // Decrement the hookcount for consistency, but always do the call. | ||
1829 | | ldr CARG2, [DISPATCH, #DISPATCH_GL(hookcount)] | ||
1830 | | tst CARG1, #HOOK_ACTIVE | ||
1831 | | bne >1 | ||
1832 | | sub CARG2, CARG2, #1 | ||
1833 | | tst CARG1, #LUA_MASKLINE|LUA_MASKCOUNT | ||
1834 | | strne CARG2, [DISPATCH, #DISPATCH_GL(hookcount)] | ||
1835 | | b >1 | ||
1815 | #endif | 1836 | #endif |
1816 | | | 1837 | | |
1817 | |->vm_rethook: // Dispatch target for return hooks. | 1838 | |->vm_rethook: // Dispatch target for return hooks. |
@@ -1860,7 +1881,18 @@ static void build_subroutines(BuildCtx *ctx) | |||
1860 | | | 1881 | | |
1861 | |->vm_hotloop: // Hot loop counter underflow. | 1882 | |->vm_hotloop: // Hot loop counter underflow. |
1862 | #if LJ_HASJIT | 1883 | #if LJ_HASJIT |
1863 | | NYI | 1884 | | ldr LFUNC:CARG3, [BASE, FRAME_FUNC] // Same as curr_topL(L). |
1885 | | sub CARG1, DISPATCH, #-GG_DISP2J | ||
1886 | | str PC, SAVE_PC | ||
1887 | | ldr CARG3, LFUNC:CARG3->field_pc | ||
1888 | | mov CARG2, PC | ||
1889 | | str L, [DISPATCH, #DISPATCH_J(L)] | ||
1890 | | ldrb CARG3, [CARG3, #PC2PROTO(framesize)] | ||
1891 | | str BASE, L->base | ||
1892 | | add CARG3, BASE, CARG3, lsl #3 | ||
1893 | | str CARG3, L->top | ||
1894 | | bl extern lj_trace_hot // (jit_State *J, const BCIns *pc) | ||
1895 | | b <3 | ||
1864 | #endif | 1896 | #endif |
1865 | | | 1897 | | |
1866 | |->vm_callhook: // Dispatch target for call hooks. | 1898 | |->vm_callhook: // Dispatch target for call hooks. |
@@ -3510,7 +3542,9 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop) | |||
3510 | | // RA = base*8, RC = target (after end of loop or start of loop) | 3542 | | // RA = base*8, RC = target (after end of loop or start of loop) |
3511 | vk = (op == BC_IFORL || op == BC_JFORL); | 3543 | vk = (op == BC_IFORL || op == BC_JFORL); |
3512 | | ldrd CARG12, [RA, BASE]! | 3544 | | ldrd CARG12, [RA, BASE]! |
3513 | | add RC, PC, RC, lsl #2 | 3545 | if (op != BC_JFORL) { |
3546 | | add RC, PC, RC, lsl #2 | ||
3547 | } | ||
3514 | if (!vk) { | 3548 | if (!vk) { |
3515 | | ldrd CARG34, FOR_STOP | 3549 | | ldrd CARG34, FOR_STOP |
3516 | | checktp CARG2, LJ_TISNUM | 3550 | | checktp CARG2, LJ_TISNUM |
@@ -3532,7 +3566,7 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop) | |||
3532 | if (op == BC_IFORL) { | 3566 | if (op == BC_IFORL) { |
3533 | | addvs RC, PC, #0x20000 // Overflow: prevent branch. | 3567 | | addvs RC, PC, #0x20000 // Overflow: prevent branch. |
3534 | } else { | 3568 | } else { |
3535 | | NYI | 3569 | | bvs >2 // Overflow: do not enter mcode. |
3536 | } | 3570 | } |
3537 | | cmp CARG3, #0 | 3571 | | cmp CARG3, #0 |
3538 | | blt >4 | 3572 | | blt >4 |
@@ -3542,15 +3576,18 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop) | |||
3542 | if (op == BC_FORI) { | 3576 | if (op == BC_FORI) { |
3543 | | subgt PC, RC, #0x20000 | 3577 | | subgt PC, RC, #0x20000 |
3544 | } else if (op == BC_JFORI) { | 3578 | } else if (op == BC_JFORI) { |
3545 | | NYI | 3579 | | subgt PC, RC, #0x20000 |
3580 | | decode_RD RC, INS | ||
3581 | | ble =>BC_JLOOP | ||
3546 | } else if (op == BC_IFORL) { | 3582 | } else if (op == BC_IFORL) { |
3547 | | suble PC, RC, #0x20000 | 3583 | | suble PC, RC, #0x20000 |
3548 | } else { | 3584 | } else { |
3549 | | NYI | 3585 | | ble =>BC_JLOOP |
3550 | } | 3586 | } |
3551 | if (vk) { | 3587 | if (vk) { |
3552 | | strd CARG12, FOR_IDX | 3588 | | strd CARG12, FOR_IDX |
3553 | } | 3589 | } |
3590 | |2: | ||
3554 | | ins_next1 | 3591 | | ins_next1 |
3555 | | ins_next2 | 3592 | | ins_next2 |
3556 | | strd CARG12, FOR_EXT | 3593 | | strd CARG12, FOR_EXT |
@@ -3587,11 +3624,13 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop) | |||
3587 | if (op == BC_FORI) { | 3624 | if (op == BC_FORI) { |
3588 | | subhi PC, RC, #0x20000 | 3625 | | subhi PC, RC, #0x20000 |
3589 | } else if (op == BC_JFORI) { | 3626 | } else if (op == BC_JFORI) { |
3590 | | NYI | 3627 | | subhi PC, RC, #0x20000 |
3628 | | decode_RD RC, INS | ||
3629 | | bls =>BC_JLOOP | ||
3591 | } else if (op == BC_IFORL) { | 3630 | } else if (op == BC_IFORL) { |
3592 | | subls PC, RC, #0x20000 | 3631 | | subls PC, RC, #0x20000 |
3593 | } else { | 3632 | } else { |
3594 | | NYI | 3633 | | bls =>BC_JLOOP |
3595 | } | 3634 | } |
3596 | | ins_next1 | 3635 | | ins_next1 |
3597 | | ins_next2 | 3636 | | ins_next2 |
@@ -3624,7 +3663,9 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop) | |||
3624 | | // RA = base*8, RC = target | 3663 | | // RA = base*8, RC = target |
3625 | | ldrd CARG12, [RA, BASE]! | 3664 | | ldrd CARG12, [RA, BASE]! |
3626 | if (op == BC_JITERL) { | 3665 | if (op == BC_JITERL) { |
3627 | | NYI | 3666 | | cmn CARG2, #-LJ_TNIL // Stop if iterator returned nil. |
3667 | | strdne CARG12, [RA, #-8] | ||
3668 | | bne =>BC_JLOOP | ||
3628 | } else { | 3669 | } else { |
3629 | | add RC, PC, RC, lsl #2 | 3670 | | add RC, PC, RC, lsl #2 |
3630 | | // STALL: load CARG12. | 3671 | | // STALL: load CARG12. |
@@ -3652,7 +3693,13 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop) | |||
3652 | 3693 | ||
3653 | case BC_JLOOP: | 3694 | case BC_JLOOP: |
3654 | #if LJ_HASJIT | 3695 | #if LJ_HASJIT |
3655 | | NYI | 3696 | | // RA = base (ignored), RC = traceno |
3697 | | ldr CARG1, [DISPATCH, #DISPATCH_J(trace)] | ||
3698 | | ldr TRACE:RC, [CARG1, RC, lsl #2] | ||
3699 | | ldr RA, TRACE:RC->mcode | ||
3700 | | str BASE, [DISPATCH, #DISPATCH_GL(jit_base)] | ||
3701 | | str L, [DISPATCH, #DISPATCH_GL(jit_L)] | ||
3702 | | bx RA | ||
3656 | #endif | 3703 | #endif |
3657 | break; | 3704 | break; |
3658 | 3705 | ||
@@ -3691,7 +3738,8 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop) | |||
3691 | | mvn CARG4, #~LJ_TNIL | 3738 | | mvn CARG4, #~LJ_TNIL |
3692 | | ble >3 | 3739 | | ble >3 |
3693 | if (op == BC_JFUNCF) { | 3740 | if (op == BC_JFUNCF) { |
3694 | | NYI | 3741 | | decode_RD RC, INS |
3742 | | b =>BC_JLOOP | ||
3695 | } else { | 3743 | } else { |
3696 | | ins_next3 | 3744 | | ins_next3 |
3697 | } | 3745 | } |