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author | Mike Pall <mike> | 2011-06-22 20:38:07 +0200 |
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committer | Mike Pall <mike> | 2011-06-22 20:38:07 +0200 |
commit | d4da9ff55ef01019c55246cd41ccd7510505cfe1 (patch) | |
tree | bffbf42dbcf73b453247be9c6b002a0a2342e3b5 /src | |
parent | e2246db688382ed69e5929f1e698b545e58b5035 (diff) | |
download | luajit-d4da9ff55ef01019c55246cd41ccd7510505cfe1.tar.gz luajit-d4da9ff55ef01019c55246cd41ccd7510505cfe1.tar.bz2 luajit-d4da9ff55ef01019c55246cd41ccd7510505cfe1.zip |
x86/x64: Fix register allocation for variable shifts.
Diffstat (limited to 'src')
-rw-r--r-- | src/lj_asm_x86.h | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/lj_asm_x86.h b/src/lj_asm_x86.h index ba28792d..da818c68 100644 --- a/src/lj_asm_x86.h +++ b/src/lj_asm_x86.h | |||
@@ -1878,15 +1878,17 @@ static void asm_bitshift(ASMState *as, IRIns *ir, x86Shift xs) | |||
1878 | default: emit_shifti(as, REX_64IR(ir, xs), dest, shift); break; | 1878 | default: emit_shifti(as, REX_64IR(ir, xs), dest, shift); break; |
1879 | } | 1879 | } |
1880 | } else { /* Variable shifts implicitly use register cl (i.e. ecx). */ | 1880 | } else { /* Variable shifts implicitly use register cl (i.e. ecx). */ |
1881 | RegSet allow = rset_exclude(RSET_GPR, RID_ECX); | 1881 | Reg right; |
1882 | Reg right = irr->r; | 1882 | dest = ra_dest(as, ir, rset_exclude(RSET_GPR, RID_ECX)); |
1883 | if (ra_noreg(right)) { | 1883 | if (dest == RID_ECX) { |
1884 | dest = ra_scratch(as, rset_exclude(RSET_GPR, RID_ECX)); | ||
1885 | emit_rr(as, XO_MOV, RID_ECX, dest); | ||
1886 | } | ||
1887 | right = irr->r; | ||
1888 | if (ra_noreg(right)) | ||
1884 | right = ra_allocref(as, rref, RID2RSET(RID_ECX)); | 1889 | right = ra_allocref(as, rref, RID2RSET(RID_ECX)); |
1885 | } else if (right != RID_ECX) { | 1890 | else if (right != RID_ECX) |
1886 | rset_clear(allow, right); | ||
1887 | ra_scratch(as, RID2RSET(RID_ECX)); | 1891 | ra_scratch(as, RID2RSET(RID_ECX)); |
1888 | } | ||
1889 | dest = ra_dest(as, ir, allow); | ||
1890 | emit_rr(as, XO_SHIFTcl, REX_64IR(ir, xs), dest); | 1892 | emit_rr(as, XO_SHIFTcl, REX_64IR(ir, xs), dest); |
1891 | if (right != RID_ECX) { | 1893 | if (right != RID_ECX) { |
1892 | ra_noweak(as, right); | 1894 | ra_noweak(as, right); |