aboutsummaryrefslogtreecommitdiff
path: root/src/lj_asm_arm64.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/lj_asm_arm64.h')
-rw-r--r--src/lj_asm_arm64.h2043
1 files changed, 2043 insertions, 0 deletions
diff --git a/src/lj_asm_arm64.h b/src/lj_asm_arm64.h
new file mode 100644
index 00000000..ce2100c9
--- /dev/null
+++ b/src/lj_asm_arm64.h
@@ -0,0 +1,2043 @@
1/*
2** ARM64 IR assembler (SSA IR -> machine code).
3** Copyright (C) 2005-2020 Mike Pall. See Copyright Notice in luajit.h
4**
5** Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
6** Sponsored by Cisco Systems, Inc.
7*/
8
9/* -- Register allocator extensions --------------------------------------- */
10
11/* Allocate a register with a hint. */
12static Reg ra_hintalloc(ASMState *as, IRRef ref, Reg hint, RegSet allow)
13{
14 Reg r = IR(ref)->r;
15 if (ra_noreg(r)) {
16 if (!ra_hashint(r) && !iscrossref(as, ref))
17 ra_sethint(IR(ref)->r, hint); /* Propagate register hint. */
18 r = ra_allocref(as, ref, allow);
19 }
20 ra_noweak(as, r);
21 return r;
22}
23
24/* Allocate two source registers for three-operand instructions. */
25static Reg ra_alloc2(ASMState *as, IRIns *ir, RegSet allow)
26{
27 IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
28 Reg left = irl->r, right = irr->r;
29 if (ra_hasreg(left)) {
30 ra_noweak(as, left);
31 if (ra_noreg(right))
32 right = ra_allocref(as, ir->op2, rset_exclude(allow, left));
33 else
34 ra_noweak(as, right);
35 } else if (ra_hasreg(right)) {
36 ra_noweak(as, right);
37 left = ra_allocref(as, ir->op1, rset_exclude(allow, right));
38 } else if (ra_hashint(right)) {
39 right = ra_allocref(as, ir->op2, allow);
40 left = ra_alloc1(as, ir->op1, rset_exclude(allow, right));
41 } else {
42 left = ra_allocref(as, ir->op1, allow);
43 right = ra_alloc1(as, ir->op2, rset_exclude(allow, left));
44 }
45 return left | (right << 8);
46}
47
48/* -- Guard handling ------------------------------------------------------ */
49
50/* Setup all needed exit stubs. */
51static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
52{
53 ExitNo i;
54 MCode *mxp = as->mctop;
55 if (mxp - (nexits + 3 + MCLIM_REDZONE) < as->mclim)
56 asm_mclimit(as);
57 /* 1: str lr,[sp]; bl ->vm_exit_handler; movz w0,traceno; bl <1; bl <1; ... */
58 for (i = nexits-1; (int32_t)i >= 0; i--)
59 *--mxp = A64I_LE(A64I_BL | A64F_S26(-3-i));
60 *--mxp = A64I_LE(A64I_MOVZw | A64F_U16(as->T->traceno));
61 mxp--;
62 *mxp = A64I_LE(A64I_BL | A64F_S26(((MCode *)(void *)lj_vm_exit_handler-mxp)));
63 *--mxp = A64I_LE(A64I_STRx | A64F_D(RID_LR) | A64F_N(RID_SP));
64 as->mctop = mxp;
65}
66
67static MCode *asm_exitstub_addr(ASMState *as, ExitNo exitno)
68{
69 /* Keep this in-sync with exitstub_trace_addr(). */
70 return as->mctop + exitno + 3;
71}
72
73/* Emit conditional branch to exit for guard. */
74static void asm_guardcc(ASMState *as, A64CC cc)
75{
76 MCode *target = asm_exitstub_addr(as, as->snapno);
77 MCode *p = as->mcp;
78 if (LJ_UNLIKELY(p == as->invmcp)) {
79 as->loopinv = 1;
80 *p = A64I_B | A64F_S26(target-p);
81 emit_cond_branch(as, cc^1, p-1);
82 return;
83 }
84 emit_cond_branch(as, cc, target);
85}
86
87/* Emit test and branch instruction to exit for guard. */
88static void asm_guardtnb(ASMState *as, A64Ins ai, Reg r, uint32_t bit)
89{
90 MCode *target = asm_exitstub_addr(as, as->snapno);
91 MCode *p = as->mcp;
92 if (LJ_UNLIKELY(p == as->invmcp)) {
93 as->loopinv = 1;
94 *p = A64I_B | A64F_S26(target-p);
95 emit_tnb(as, ai^0x01000000u, r, bit, p-1);
96 return;
97 }
98 emit_tnb(as, ai, r, bit, target);
99}
100
101/* Emit compare and branch instruction to exit for guard. */
102static void asm_guardcnb(ASMState *as, A64Ins ai, Reg r)
103{
104 MCode *target = asm_exitstub_addr(as, as->snapno);
105 MCode *p = as->mcp;
106 if (LJ_UNLIKELY(p == as->invmcp)) {
107 as->loopinv = 1;
108 *p = A64I_B | A64F_S26(target-p);
109 emit_cnb(as, ai^0x01000000u, r, p-1);
110 return;
111 }
112 emit_cnb(as, ai, r, target);
113}
114
115/* -- Operand fusion ------------------------------------------------------ */
116
117/* Limit linear search to this distance. Avoids O(n^2) behavior. */
118#define CONFLICT_SEARCH_LIM 31
119
120static int asm_isk32(ASMState *as, IRRef ref, int32_t *k)
121{
122 if (irref_isk(ref)) {
123 IRIns *ir = IR(ref);
124 if (ir->o == IR_KNULL || !irt_is64(ir->t)) {
125 *k = ir->i;
126 return 1;
127 } else if (checki32((int64_t)ir_k64(ir)->u64)) {
128 *k = (int32_t)ir_k64(ir)->u64;
129 return 1;
130 }
131 }
132 return 0;
133}
134
135/* Check if there's no conflicting instruction between curins and ref. */
136static int noconflict(ASMState *as, IRRef ref, IROp conflict)
137{
138 IRIns *ir = as->ir;
139 IRRef i = as->curins;
140 if (i > ref + CONFLICT_SEARCH_LIM)
141 return 0; /* Give up, ref is too far away. */
142 while (--i > ref)
143 if (ir[i].o == conflict)
144 return 0; /* Conflict found. */
145 return 1; /* Ok, no conflict. */
146}
147
148/* Fuse the array base of colocated arrays. */
149static int32_t asm_fuseabase(ASMState *as, IRRef ref)
150{
151 IRIns *ir = IR(ref);
152 if (ir->o == IR_TNEW && ir->op1 <= LJ_MAX_COLOSIZE &&
153 !neverfuse(as) && noconflict(as, ref, IR_NEWREF))
154 return (int32_t)sizeof(GCtab);
155 return 0;
156}
157
158#define FUSE_REG 0x40000000
159
160/* Fuse array/hash/upvalue reference into register+offset operand. */
161static Reg asm_fuseahuref(ASMState *as, IRRef ref, int32_t *ofsp, RegSet allow,
162 A64Ins ins)
163{
164 IRIns *ir = IR(ref);
165 if (ra_noreg(ir->r)) {
166 if (ir->o == IR_AREF) {
167 if (mayfuse(as, ref)) {
168 if (irref_isk(ir->op2)) {
169 IRRef tab = IR(ir->op1)->op1;
170 int32_t ofs = asm_fuseabase(as, tab);
171 IRRef refa = ofs ? tab : ir->op1;
172 ofs += 8*IR(ir->op2)->i;
173 if (emit_checkofs(ins, ofs)) {
174 *ofsp = ofs;
175 return ra_alloc1(as, refa, allow);
176 }
177 } else {
178 Reg base = ra_alloc1(as, ir->op1, allow);
179 *ofsp = FUSE_REG|ra_alloc1(as, ir->op2, rset_exclude(allow, base));
180 return base;
181 }
182 }
183 } else if (ir->o == IR_HREFK) {
184 if (mayfuse(as, ref)) {
185 int32_t ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
186 if (emit_checkofs(ins, ofs)) {
187 *ofsp = ofs;
188 return ra_alloc1(as, ir->op1, allow);
189 }
190 }
191 } else if (ir->o == IR_UREFC) {
192 if (irref_isk(ir->op1)) {
193 GCfunc *fn = ir_kfunc(IR(ir->op1));
194 GCupval *uv = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv;
195 int64_t ofs = glofs(as, &uv->tv);
196 if (emit_checkofs(ins, ofs)) {
197 *ofsp = (int32_t)ofs;
198 return RID_GL;
199 }
200 }
201 }
202 }
203 *ofsp = 0;
204 return ra_alloc1(as, ref, allow);
205}
206
207/* Fuse m operand into arithmetic/logic instructions. */
208static uint32_t asm_fuseopm(ASMState *as, A64Ins ai, IRRef ref, RegSet allow)
209{
210 IRIns *ir = IR(ref);
211 if (ra_hasreg(ir->r)) {
212 ra_noweak(as, ir->r);
213 return A64F_M(ir->r);
214 } else if (irref_isk(ref)) {
215 uint32_t m;
216 int64_t k = get_k64val(ir);
217 if ((ai & 0x1f000000) == 0x0a000000)
218 m = emit_isk13(k, irt_is64(ir->t));
219 else
220 m = emit_isk12(k);
221 if (m)
222 return m;
223 } else if (mayfuse(as, ref)) {
224 if ((ir->o >= IR_BSHL && ir->o <= IR_BSAR && irref_isk(ir->op2)) ||
225 (ir->o == IR_ADD && ir->op1 == ir->op2)) {
226 A64Shift sh = ir->o == IR_BSHR ? A64SH_LSR :
227 ir->o == IR_BSAR ? A64SH_ASR : A64SH_LSL;
228 int shift = ir->o == IR_ADD ? 1 :
229 (IR(ir->op2)->i & (irt_is64(ir->t) ? 63 : 31));
230 IRIns *irl = IR(ir->op1);
231 if (sh == A64SH_LSL &&
232 irl->o == IR_CONV &&
233 irl->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT) &&
234 shift <= 4 &&
235 canfuse(as, irl)) {
236 Reg m = ra_alloc1(as, irl->op1, allow);
237 return A64F_M(m) | A64F_EXSH(A64EX_SXTW, shift);
238 } else {
239 Reg m = ra_alloc1(as, ir->op1, allow);
240 return A64F_M(m) | A64F_SH(sh, shift);
241 }
242 } else if (ir->o == IR_CONV &&
243 ir->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT)) {
244 Reg m = ra_alloc1(as, ir->op1, allow);
245 return A64F_M(m) | A64F_EX(A64EX_SXTW);
246 }
247 }
248 return A64F_M(ra_allocref(as, ref, allow));
249}
250
251/* Fuse XLOAD/XSTORE reference into load/store operand. */
252static void asm_fusexref(ASMState *as, A64Ins ai, Reg rd, IRRef ref,
253 RegSet allow)
254{
255 IRIns *ir = IR(ref);
256 Reg base;
257 int32_t ofs = 0;
258 if (ra_noreg(ir->r) && canfuse(as, ir)) {
259 if (ir->o == IR_ADD) {
260 if (asm_isk32(as, ir->op2, &ofs) && emit_checkofs(ai, ofs)) {
261 ref = ir->op1;
262 } else {
263 Reg rn, rm;
264 IRRef lref = ir->op1, rref = ir->op2;
265 IRIns *irl = IR(lref);
266 if (mayfuse(as, irl->op1)) {
267 unsigned int shift = 4;
268 if (irl->o == IR_BSHL && irref_isk(irl->op2)) {
269 shift = (IR(irl->op2)->i & 63);
270 } else if (irl->o == IR_ADD && irl->op1 == irl->op2) {
271 shift = 1;
272 }
273 if ((ai >> 30) == shift) {
274 lref = irl->op1;
275 irl = IR(lref);
276 ai |= A64I_LS_SH;
277 }
278 }
279 if (irl->o == IR_CONV &&
280 irl->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT) &&
281 canfuse(as, irl)) {
282 lref = irl->op1;
283 ai |= A64I_LS_SXTWx;
284 } else {
285 ai |= A64I_LS_LSLx;
286 }
287 rm = ra_alloc1(as, lref, allow);
288 rn = ra_alloc1(as, rref, rset_exclude(allow, rm));
289 emit_dnm(as, (ai^A64I_LS_R), (rd & 31), rn, rm);
290 return;
291 }
292 } else if (ir->o == IR_STRREF) {
293 if (asm_isk32(as, ir->op2, &ofs)) {
294 ref = ir->op1;
295 } else if (asm_isk32(as, ir->op1, &ofs)) {
296 ref = ir->op2;
297 } else {
298 Reg refk = irref_isk(ir->op1) ? ir->op1 : ir->op2;
299 Reg refv = irref_isk(ir->op1) ? ir->op2 : ir->op1;
300 Reg rn = ra_alloc1(as, refv, allow);
301 IRIns *irr = IR(refk);
302 uint32_t m;
303 if (irr+1 == ir && !ra_used(irr) &&
304 irr->o == IR_ADD && irref_isk(irr->op2)) {
305 ofs = sizeof(GCstr) + IR(irr->op2)->i;
306 if (emit_checkofs(ai, ofs)) {
307 Reg rm = ra_alloc1(as, irr->op1, rset_exclude(allow, rn));
308 m = A64F_M(rm) | A64F_EX(A64EX_SXTW);
309 goto skipopm;
310 }
311 }
312 m = asm_fuseopm(as, 0, refk, rset_exclude(allow, rn));
313 ofs = sizeof(GCstr);
314 skipopm:
315 emit_lso(as, ai, rd, rd, ofs);
316 emit_dn(as, A64I_ADDx^m, rd, rn);
317 return;
318 }
319 ofs += sizeof(GCstr);
320 if (!emit_checkofs(ai, ofs)) {
321 Reg rn = ra_alloc1(as, ref, allow);
322 Reg rm = ra_allock(as, ofs, rset_exclude(allow, rn));
323 emit_dnm(as, (ai^A64I_LS_R)|A64I_LS_UXTWx, rd, rn, rm);
324 return;
325 }
326 }
327 }
328 base = ra_alloc1(as, ref, allow);
329 emit_lso(as, ai, (rd & 31), base, ofs);
330}
331
332/* Fuse FP multiply-add/sub. */
333static int asm_fusemadd(ASMState *as, IRIns *ir, A64Ins ai, A64Ins air)
334{
335 IRRef lref = ir->op1, rref = ir->op2;
336 IRIns *irm;
337 if (lref != rref &&
338 ((mayfuse(as, lref) && (irm = IR(lref), irm->o == IR_MUL) &&
339 ra_noreg(irm->r)) ||
340 (mayfuse(as, rref) && (irm = IR(rref), irm->o == IR_MUL) &&
341 (rref = lref, ai = air, ra_noreg(irm->r))))) {
342 Reg dest = ra_dest(as, ir, RSET_FPR);
343 Reg add = ra_hintalloc(as, rref, dest, RSET_FPR);
344 Reg left = ra_alloc2(as, irm,
345 rset_exclude(rset_exclude(RSET_FPR, dest), add));
346 Reg right = (left >> 8); left &= 255;
347 emit_dnma(as, ai, (dest & 31), (left & 31), (right & 31), (add & 31));
348 return 1;
349 }
350 return 0;
351}
352
353/* Fuse BAND + BSHL/BSHR into UBFM. */
354static int asm_fuseandshift(ASMState *as, IRIns *ir)
355{
356 IRIns *irl = IR(ir->op1);
357 lua_assert(ir->o == IR_BAND);
358 if (canfuse(as, irl) && irref_isk(ir->op2)) {
359 uint64_t mask = get_k64val(IR(ir->op2));
360 if (irref_isk(irl->op2) && (irl->o == IR_BSHR || irl->o == IR_BSHL)) {
361 int32_t shmask = irt_is64(irl->t) ? 63 : 31;
362 int32_t shift = (IR(irl->op2)->i & shmask);
363 int32_t imms = shift;
364 if (irl->o == IR_BSHL) {
365 mask >>= shift;
366 shift = (shmask-shift+1) & shmask;
367 imms = 0;
368 }
369 if (mask && !((mask+1) & mask)) { /* Contiguous 1-bits at the bottom. */
370 Reg dest = ra_dest(as, ir, RSET_GPR);
371 Reg left = ra_alloc1(as, irl->op1, RSET_GPR);
372 A64Ins ai = shmask == 63 ? A64I_UBFMx : A64I_UBFMw;
373 imms += 63 - emit_clz64(mask);
374 if (imms > shmask) imms = shmask;
375 emit_dn(as, ai | A64F_IMMS(imms) | A64F_IMMR(shift), dest, left);
376 return 1;
377 }
378 }
379 }
380 return 0;
381}
382
383/* Fuse BOR(BSHL, BSHR) into EXTR/ROR. */
384static int asm_fuseorshift(ASMState *as, IRIns *ir)
385{
386 IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
387 lua_assert(ir->o == IR_BOR);
388 if (canfuse(as, irl) && canfuse(as, irr) &&
389 ((irl->o == IR_BSHR && irr->o == IR_BSHL) ||
390 (irl->o == IR_BSHL && irr->o == IR_BSHR))) {
391 if (irref_isk(irl->op2) && irref_isk(irr->op2)) {
392 IRRef lref = irl->op1, rref = irr->op1;
393 uint32_t lshift = IR(irl->op2)->i, rshift = IR(irr->op2)->i;
394 if (irl->o == IR_BSHR) { /* BSHR needs to be the right operand. */
395 uint32_t tmp2;
396 IRRef tmp1 = lref; lref = rref; rref = tmp1;
397 tmp2 = lshift; lshift = rshift; rshift = tmp2;
398 }
399 if (rshift + lshift == (irt_is64(ir->t) ? 64 : 32)) {
400 A64Ins ai = irt_is64(ir->t) ? A64I_EXTRx : A64I_EXTRw;
401 Reg dest = ra_dest(as, ir, RSET_GPR);
402 Reg left = ra_alloc1(as, lref, RSET_GPR);
403 Reg right = ra_alloc1(as, rref, rset_exclude(RSET_GPR, left));
404 emit_dnm(as, ai | A64F_IMMS(rshift), dest, left, right);
405 return 1;
406 }
407 }
408 }
409 return 0;
410}
411
412/* -- Calls --------------------------------------------------------------- */
413
414/* Generate a call to a C function. */
415static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
416{
417 uint32_t n, nargs = CCI_XNARGS(ci);
418 int32_t ofs = 0;
419 Reg gpr, fpr = REGARG_FIRSTFPR;
420 if ((void *)ci->func)
421 emit_call(as, (void *)ci->func);
422 for (gpr = REGARG_FIRSTGPR; gpr <= REGARG_LASTGPR; gpr++)
423 as->cost[gpr] = REGCOST(~0u, ASMREF_L);
424 gpr = REGARG_FIRSTGPR;
425 for (n = 0; n < nargs; n++) { /* Setup args. */
426 IRRef ref = args[n];
427 IRIns *ir = IR(ref);
428 if (ref) {
429 if (irt_isfp(ir->t)) {
430 if (fpr <= REGARG_LASTFPR) {
431 lua_assert(rset_test(as->freeset, fpr)); /* Must have been evicted. */
432 ra_leftov(as, fpr, ref);
433 fpr++;
434 } else {
435 Reg r = ra_alloc1(as, ref, RSET_FPR);
436 emit_spstore(as, ir, r, ofs + ((LJ_BE && !irt_isnum(ir->t)) ? 4 : 0));
437 ofs += 8;
438 }
439 } else {
440 if (gpr <= REGARG_LASTGPR) {
441 lua_assert(rset_test(as->freeset, gpr)); /* Must have been evicted. */
442 ra_leftov(as, gpr, ref);
443 gpr++;
444 } else {
445 Reg r = ra_alloc1(as, ref, RSET_GPR);
446 emit_spstore(as, ir, r, ofs + ((LJ_BE && !irt_is64(ir->t)) ? 4 : 0));
447 ofs += 8;
448 }
449 }
450 }
451 }
452}
453
454/* Setup result reg/sp for call. Evict scratch regs. */
455static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
456{
457 RegSet drop = RSET_SCRATCH;
458 if (ra_hasreg(ir->r))
459 rset_clear(drop, ir->r); /* Dest reg handled below. */
460 ra_evictset(as, drop); /* Evictions must be performed first. */
461 if (ra_used(ir)) {
462 lua_assert(!irt_ispri(ir->t));
463 if (irt_isfp(ir->t)) {
464 if (ci->flags & CCI_CASTU64) {
465 Reg dest = ra_dest(as, ir, RSET_FPR) & 31;
466 emit_dn(as, irt_isnum(ir->t) ? A64I_FMOV_D_R : A64I_FMOV_S_R,
467 dest, RID_RET);
468 } else {
469 ra_destreg(as, ir, RID_FPRET);
470 }
471 } else {
472 ra_destreg(as, ir, RID_RET);
473 }
474 }
475 UNUSED(ci);
476}
477
478static void asm_callx(ASMState *as, IRIns *ir)
479{
480 IRRef args[CCI_NARGS_MAX*2];
481 CCallInfo ci;
482 IRRef func;
483 IRIns *irf;
484 ci.flags = asm_callx_flags(as, ir);
485 asm_collectargs(as, ir, &ci, args);
486 asm_setupresult(as, ir, &ci);
487 func = ir->op2; irf = IR(func);
488 if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
489 if (irref_isk(func)) { /* Call to constant address. */
490 ci.func = (ASMFunction)(ir_k64(irf)->u64);
491 } else { /* Need a non-argument register for indirect calls. */
492 Reg freg = ra_alloc1(as, func, RSET_RANGE(RID_X8, RID_MAX_GPR)-RSET_FIXED);
493 emit_n(as, A64I_BLR, freg);
494 ci.func = (ASMFunction)(void *)0;
495 }
496 asm_gencall(as, &ci, args);
497}
498
499/* -- Returns ------------------------------------------------------------- */
500
501/* Return to lower frame. Guard that it goes to the right spot. */
502static void asm_retf(ASMState *as, IRIns *ir)
503{
504 Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
505 void *pc = ir_kptr(IR(ir->op2));
506 int32_t delta = 1+LJ_FR2+bc_a(*((const BCIns *)pc - 1));
507 as->topslot -= (BCReg)delta;
508 if ((int32_t)as->topslot < 0) as->topslot = 0;
509 irt_setmark(IR(REF_BASE)->t); /* Children must not coalesce with BASE reg. */
510 /* Need to force a spill on REF_BASE now to update the stack slot. */
511 emit_lso(as, A64I_STRx, base, RID_SP, ra_spill(as, IR(REF_BASE)));
512 emit_setgl(as, base, jit_base);
513 emit_addptr(as, base, -8*delta);
514 asm_guardcc(as, CC_NE);
515 emit_nm(as, A64I_CMPx, RID_TMP,
516 ra_allock(as, i64ptr(pc), rset_exclude(RSET_GPR, base)));
517 emit_lso(as, A64I_LDRx, RID_TMP, base, -8);
518}
519
520/* -- Type conversions ---------------------------------------------------- */
521
522static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
523{
524 Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
525 Reg dest = ra_dest(as, ir, RSET_GPR);
526 asm_guardcc(as, CC_NE);
527 emit_nm(as, A64I_FCMPd, (tmp & 31), (left & 31));
528 emit_dn(as, A64I_FCVT_F64_S32, (tmp & 31), dest);
529 emit_dn(as, A64I_FCVT_S32_F64, dest, (left & 31));
530}
531
532static void asm_tobit(ASMState *as, IRIns *ir)
533{
534 RegSet allow = RSET_FPR;
535 Reg left = ra_alloc1(as, ir->op1, allow);
536 Reg right = ra_alloc1(as, ir->op2, rset_clear(allow, left));
537 Reg tmp = ra_scratch(as, rset_clear(allow, right));
538 Reg dest = ra_dest(as, ir, RSET_GPR);
539 emit_dn(as, A64I_FMOV_R_S, dest, (tmp & 31));
540 emit_dnm(as, A64I_FADDd, (tmp & 31), (left & 31), (right & 31));
541}
542
543static void asm_conv(ASMState *as, IRIns *ir)
544{
545 IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
546 int st64 = (st == IRT_I64 || st == IRT_U64 || st == IRT_P64);
547 int stfp = (st == IRT_NUM || st == IRT_FLOAT);
548 IRRef lref = ir->op1;
549 lua_assert(irt_type(ir->t) != st);
550 if (irt_isfp(ir->t)) {
551 Reg dest = ra_dest(as, ir, RSET_FPR);
552 if (stfp) { /* FP to FP conversion. */
553 emit_dn(as, st == IRT_NUM ? A64I_FCVT_F32_F64 : A64I_FCVT_F64_F32,
554 (dest & 31), (ra_alloc1(as, lref, RSET_FPR) & 31));
555 } else { /* Integer to FP conversion. */
556 Reg left = ra_alloc1(as, lref, RSET_GPR);
557 A64Ins ai = irt_isfloat(ir->t) ?
558 (((IRT_IS64 >> st) & 1) ?
559 (st == IRT_I64 ? A64I_FCVT_F32_S64 : A64I_FCVT_F32_U64) :
560 (st == IRT_INT ? A64I_FCVT_F32_S32 : A64I_FCVT_F32_U32)) :
561 (((IRT_IS64 >> st) & 1) ?
562 (st == IRT_I64 ? A64I_FCVT_F64_S64 : A64I_FCVT_F64_U64) :
563 (st == IRT_INT ? A64I_FCVT_F64_S32 : A64I_FCVT_F64_U32));
564 emit_dn(as, ai, (dest & 31), left);
565 }
566 } else if (stfp) { /* FP to integer conversion. */
567 if (irt_isguard(ir->t)) {
568 /* Checked conversions are only supported from number to int. */
569 lua_assert(irt_isint(ir->t) && st == IRT_NUM);
570 asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
571 } else {
572 Reg left = ra_alloc1(as, lref, RSET_FPR);
573 Reg dest = ra_dest(as, ir, RSET_GPR);
574 A64Ins ai = irt_is64(ir->t) ?
575 (st == IRT_NUM ?
576 (irt_isi64(ir->t) ? A64I_FCVT_S64_F64 : A64I_FCVT_U64_F64) :
577 (irt_isi64(ir->t) ? A64I_FCVT_S64_F32 : A64I_FCVT_U64_F32)) :
578 (st == IRT_NUM ?
579 (irt_isint(ir->t) ? A64I_FCVT_S32_F64 : A64I_FCVT_U32_F64) :
580 (irt_isint(ir->t) ? A64I_FCVT_S32_F32 : A64I_FCVT_U32_F32));
581 emit_dn(as, ai, dest, (left & 31));
582 }
583 } else if (st >= IRT_I8 && st <= IRT_U16) { /* Extend to 32 bit integer. */
584 Reg dest = ra_dest(as, ir, RSET_GPR);
585 Reg left = ra_alloc1(as, lref, RSET_GPR);
586 A64Ins ai = st == IRT_I8 ? A64I_SXTBw :
587 st == IRT_U8 ? A64I_UXTBw :
588 st == IRT_I16 ? A64I_SXTHw : A64I_UXTHw;
589 lua_assert(irt_isint(ir->t) || irt_isu32(ir->t));
590 emit_dn(as, ai, dest, left);
591 } else {
592 Reg dest = ra_dest(as, ir, RSET_GPR);
593 if (irt_is64(ir->t)) {
594 if (st64 || !(ir->op2 & IRCONV_SEXT)) {
595 /* 64/64 bit no-op (cast) or 32 to 64 bit zero extension. */
596 ra_leftov(as, dest, lref); /* Do nothing, but may need to move regs. */
597 } else { /* 32 to 64 bit sign extension. */
598 Reg left = ra_alloc1(as, lref, RSET_GPR);
599 emit_dn(as, A64I_SXTW, dest, left);
600 }
601 } else {
602 if (st64) {
603 /* This is either a 32 bit reg/reg mov which zeroes the hiword
604 ** or a load of the loword from a 64 bit address.
605 */
606 Reg left = ra_alloc1(as, lref, RSET_GPR);
607 emit_dm(as, A64I_MOVw, dest, left);
608 } else { /* 32/32 bit no-op (cast). */
609 ra_leftov(as, dest, lref); /* Do nothing, but may need to move regs. */
610 }
611 }
612 }
613}
614
615static void asm_strto(ASMState *as, IRIns *ir)
616{
617 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
618 IRRef args[2];
619 Reg dest = 0, tmp;
620 int destused = ra_used(ir);
621 int32_t ofs = 0;
622 ra_evictset(as, RSET_SCRATCH);
623 if (destused) {
624 if (ra_hasspill(ir->s)) {
625 ofs = sps_scale(ir->s);
626 destused = 0;
627 if (ra_hasreg(ir->r)) {
628 ra_free(as, ir->r);
629 ra_modified(as, ir->r);
630 emit_spload(as, ir, ir->r, ofs);
631 }
632 } else {
633 dest = ra_dest(as, ir, RSET_FPR);
634 }
635 }
636 if (destused)
637 emit_lso(as, A64I_LDRd, (dest & 31), RID_SP, 0);
638 asm_guardcnb(as, A64I_CBZ, RID_RET);
639 args[0] = ir->op1; /* GCstr *str */
640 args[1] = ASMREF_TMP1; /* TValue *n */
641 asm_gencall(as, ci, args);
642 tmp = ra_releasetmp(as, ASMREF_TMP1);
643 emit_opk(as, A64I_ADDx, tmp, RID_SP, ofs, RSET_GPR);
644}
645
646/* -- Memory references --------------------------------------------------- */
647
648/* Store tagged value for ref at base+ofs. */
649static void asm_tvstore64(ASMState *as, Reg base, int32_t ofs, IRRef ref)
650{
651 RegSet allow = rset_exclude(RSET_GPR, base);
652 IRIns *ir = IR(ref);
653 lua_assert(irt_ispri(ir->t) || irt_isaddr(ir->t) || irt_isinteger(ir->t));
654 if (irref_isk(ref)) {
655 TValue k;
656 lj_ir_kvalue(as->J->L, &k, ir);
657 emit_lso(as, A64I_STRx, ra_allock(as, k.u64, allow), base, ofs);
658 } else {
659 Reg src = ra_alloc1(as, ref, allow);
660 rset_clear(allow, src);
661 if (irt_isinteger(ir->t)) {
662 Reg type = ra_allock(as, (int64_t)irt_toitype(ir->t) << 47, allow);
663 emit_lso(as, A64I_STRx, RID_TMP, base, ofs);
664 emit_dnm(as, A64I_ADDx | A64F_EX(A64EX_UXTW), RID_TMP, type, src);
665 } else {
666 Reg type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
667 emit_lso(as, A64I_STRx, RID_TMP, base, ofs);
668 emit_dnm(as, A64I_ADDx | A64F_SH(A64SH_LSL, 47), RID_TMP, src, type);
669 }
670 }
671}
672
673/* Get pointer to TValue. */
674static void asm_tvptr(ASMState *as, Reg dest, IRRef ref)
675{
676 IRIns *ir = IR(ref);
677 if (irt_isnum(ir->t)) {
678 if (irref_isk(ref)) {
679 /* Use the number constant itself as a TValue. */
680 ra_allockreg(as, i64ptr(ir_knum(ir)), dest);
681 } else {
682 /* Otherwise force a spill and use the spill slot. */
683 emit_opk(as, A64I_ADDx, dest, RID_SP, ra_spill(as, ir), RSET_GPR);
684 }
685 } else {
686 /* Otherwise use g->tmptv to hold the TValue. */
687 asm_tvstore64(as, dest, 0, ref);
688 ra_allockreg(as, i64ptr(&J2G(as->J)->tmptv), dest);
689 }
690}
691
692static void asm_aref(ASMState *as, IRIns *ir)
693{
694 Reg dest = ra_dest(as, ir, RSET_GPR);
695 Reg idx, base;
696 if (irref_isk(ir->op2)) {
697 IRRef tab = IR(ir->op1)->op1;
698 int32_t ofs = asm_fuseabase(as, tab);
699 IRRef refa = ofs ? tab : ir->op1;
700 uint32_t k = emit_isk12(ofs + 8*IR(ir->op2)->i);
701 if (k) {
702 base = ra_alloc1(as, refa, RSET_GPR);
703 emit_dn(as, A64I_ADDx^k, dest, base);
704 return;
705 }
706 }
707 base = ra_alloc1(as, ir->op1, RSET_GPR);
708 idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
709 emit_dnm(as, A64I_ADDx | A64F_EXSH(A64EX_UXTW, 3), dest, base, idx);
710}
711
712/* Inlined hash lookup. Specialized for key type and for const keys.
713** The equivalent C code is:
714** Node *n = hashkey(t, key);
715** do {
716** if (lj_obj_equal(&n->key, key)) return &n->val;
717** } while ((n = nextnode(n)));
718** return niltv(L);
719*/
720static void asm_href(ASMState *as, IRIns *ir, IROp merge)
721{
722 RegSet allow = RSET_GPR;
723 int destused = ra_used(ir);
724 Reg dest = ra_dest(as, ir, allow);
725 Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
726 Reg key = 0, tmp = RID_TMP;
727 Reg ftmp = RID_NONE, type = RID_NONE, scr = RID_NONE, tisnum = RID_NONE;
728 IRRef refkey = ir->op2;
729 IRIns *irkey = IR(refkey);
730 int isk = irref_isk(ir->op2);
731 IRType1 kt = irkey->t;
732 uint32_t k = 0;
733 uint32_t khash;
734 MCLabel l_end, l_loop, l_next;
735 rset_clear(allow, tab);
736
737 if (!isk) {
738 key = ra_alloc1(as, ir->op2, irt_isnum(kt) ? RSET_FPR : allow);
739 rset_clear(allow, key);
740 if (!irt_isstr(kt)) {
741 tmp = ra_scratch(as, allow);
742 rset_clear(allow, tmp);
743 }
744 } else if (irt_isnum(kt)) {
745 int64_t val = (int64_t)ir_knum(irkey)->u64;
746 if (!(k = emit_isk12(val))) {
747 key = ra_allock(as, val, allow);
748 rset_clear(allow, key);
749 }
750 } else if (!irt_ispri(kt)) {
751 if (!(k = emit_isk12(irkey->i))) {
752 key = ra_alloc1(as, refkey, allow);
753 rset_clear(allow, key);
754 }
755 }
756
757 /* Allocate constants early. */
758 if (irt_isnum(kt)) {
759 if (!isk) {
760 tisnum = ra_allock(as, LJ_TISNUM << 15, allow);
761 ftmp = ra_scratch(as, rset_exclude(RSET_FPR, key));
762 rset_clear(allow, tisnum);
763 }
764 } else if (irt_isaddr(kt)) {
765 if (isk) {
766 int64_t kk = ((int64_t)irt_toitype(irkey->t) << 47) | irkey[1].tv.u64;
767 scr = ra_allock(as, kk, allow);
768 } else {
769 scr = ra_scratch(as, allow);
770 }
771 rset_clear(allow, scr);
772 } else {
773 lua_assert(irt_ispri(kt) && !irt_isnil(kt));
774 type = ra_allock(as, ~((int64_t)~irt_toitype(ir->t) << 47), allow);
775 scr = ra_scratch(as, rset_clear(allow, type));
776 rset_clear(allow, scr);
777 }
778
779 /* Key not found in chain: jump to exit (if merged) or load niltv. */
780 l_end = emit_label(as);
781 as->invmcp = NULL;
782 if (merge == IR_NE)
783 asm_guardcc(as, CC_AL);
784 else if (destused)
785 emit_loada(as, dest, niltvg(J2G(as->J)));
786
787 /* Follow hash chain until the end. */
788 l_loop = --as->mcp;
789 emit_n(as, A64I_CMPx^A64I_K12^0, dest);
790 emit_lso(as, A64I_LDRx, dest, dest, offsetof(Node, next));
791 l_next = emit_label(as);
792
793 /* Type and value comparison. */
794 if (merge == IR_EQ)
795 asm_guardcc(as, CC_EQ);
796 else
797 emit_cond_branch(as, CC_EQ, l_end);
798
799 if (irt_isnum(kt)) {
800 if (isk) {
801 /* Assumes -0.0 is already canonicalized to +0.0. */
802 if (k)
803 emit_n(as, A64I_CMPx^k, tmp);
804 else
805 emit_nm(as, A64I_CMPx, key, tmp);
806 emit_lso(as, A64I_LDRx, tmp, dest, offsetof(Node, key.u64));
807 } else {
808 emit_nm(as, A64I_FCMPd, key, ftmp);
809 emit_dn(as, A64I_FMOV_D_R, (ftmp & 31), (tmp & 31));
810 emit_cond_branch(as, CC_LO, l_next);
811 emit_nm(as, A64I_CMPx | A64F_SH(A64SH_LSR, 32), tisnum, tmp);
812 emit_lso(as, A64I_LDRx, tmp, dest, offsetof(Node, key.n));
813 }
814 } else if (irt_isaddr(kt)) {
815 if (isk) {
816 emit_nm(as, A64I_CMPx, scr, tmp);
817 emit_lso(as, A64I_LDRx, tmp, dest, offsetof(Node, key.u64));
818 } else {
819 emit_nm(as, A64I_CMPx, tmp, scr);
820 emit_lso(as, A64I_LDRx, scr, dest, offsetof(Node, key.u64));
821 }
822 } else {
823 emit_nm(as, A64I_CMPw, scr, type);
824 emit_lso(as, A64I_LDRx, scr, dest, offsetof(Node, key));
825 }
826
827 *l_loop = A64I_BCC | A64F_S19(as->mcp - l_loop) | CC_NE;
828 if (!isk && irt_isaddr(kt)) {
829 type = ra_allock(as, (int32_t)irt_toitype(kt), allow);
830 emit_dnm(as, A64I_ADDx | A64F_SH(A64SH_LSL, 47), tmp, key, type);
831 rset_clear(allow, type);
832 }
833 /* Load main position relative to tab->node into dest. */
834 khash = isk ? ir_khash(irkey) : 1;
835 if (khash == 0) {
836 emit_lso(as, A64I_LDRx, dest, tab, offsetof(GCtab, node));
837 } else {
838 emit_dnm(as, A64I_ADDx | A64F_SH(A64SH_LSL, 3), dest, tmp, dest);
839 emit_dnm(as, A64I_ADDx | A64F_SH(A64SH_LSL, 1), dest, dest, dest);
840 emit_lso(as, A64I_LDRx, tmp, tab, offsetof(GCtab, node));
841 if (isk) {
842 Reg tmphash = ra_allock(as, khash, allow);
843 emit_dnm(as, A64I_ANDw, dest, dest, tmphash);
844 emit_lso(as, A64I_LDRw, dest, tab, offsetof(GCtab, hmask));
845 } else if (irt_isstr(kt)) {
846 /* Fetch of str->hash is cheaper than ra_allock. */
847 emit_dnm(as, A64I_ANDw, dest, dest, tmp);
848 emit_lso(as, A64I_LDRw, tmp, key, offsetof(GCstr, hash));
849 emit_lso(as, A64I_LDRw, dest, tab, offsetof(GCtab, hmask));
850 } else { /* Must match with hash*() in lj_tab.c. */
851 emit_dnm(as, A64I_ANDw, dest, dest, tmp);
852 emit_lso(as, A64I_LDRw, tmp, tab, offsetof(GCtab, hmask));
853 emit_dnm(as, A64I_SUBw, dest, dest, tmp);
854 emit_dnm(as, A64I_EXTRw | (A64F_IMMS(32-HASH_ROT3)), tmp, tmp, tmp);
855 emit_dnm(as, A64I_EORw, dest, dest, tmp);
856 emit_dnm(as, A64I_EXTRw | (A64F_IMMS(32-HASH_ROT2)), dest, dest, dest);
857 emit_dnm(as, A64I_SUBw, tmp, tmp, dest);
858 emit_dnm(as, A64I_EXTRw | (A64F_IMMS(32-HASH_ROT1)), dest, dest, dest);
859 emit_dnm(as, A64I_EORw, tmp, tmp, dest);
860 if (irt_isnum(kt)) {
861 emit_dnm(as, A64I_ADDw, dest, dest, dest);
862 emit_dn(as, A64I_LSRx | A64F_IMMR(32)|A64F_IMMS(32), dest, dest);
863 emit_dm(as, A64I_MOVw, tmp, dest);
864 emit_dn(as, A64I_FMOV_R_D, dest, (key & 31));
865 } else {
866 checkmclim(as);
867 emit_dm(as, A64I_MOVw, tmp, key);
868 emit_dnm(as, A64I_EORw, dest, dest,
869 ra_allock(as, irt_toitype(kt) << 15, allow));
870 emit_dn(as, A64I_LSRx | A64F_IMMR(32)|A64F_IMMS(32), dest, dest);
871 emit_dm(as, A64I_MOVx, dest, key);
872 }
873 }
874 }
875}
876
877static void asm_hrefk(ASMState *as, IRIns *ir)
878{
879 IRIns *kslot = IR(ir->op2);
880 IRIns *irkey = IR(kslot->op1);
881 int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
882 int32_t kofs = ofs + (int32_t)offsetof(Node, key);
883 int bigofs = !emit_checkofs(A64I_LDRx, ofs);
884 Reg dest = (ra_used(ir) || bigofs) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
885 Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
886 Reg key, idx = node;
887 RegSet allow = rset_exclude(RSET_GPR, node);
888 uint64_t k;
889 lua_assert(ofs % sizeof(Node) == 0);
890 if (bigofs) {
891 idx = dest;
892 rset_clear(allow, dest);
893 kofs = (int32_t)offsetof(Node, key);
894 } else if (ra_hasreg(dest)) {
895 emit_opk(as, A64I_ADDx, dest, node, ofs, allow);
896 }
897 asm_guardcc(as, CC_NE);
898 if (irt_ispri(irkey->t)) {
899 k = ~((int64_t)~irt_toitype(irkey->t) << 47);
900 } else if (irt_isnum(irkey->t)) {
901 k = ir_knum(irkey)->u64;
902 } else {
903 k = ((uint64_t)irt_toitype(irkey->t) << 47) | (uint64_t)ir_kgc(irkey);
904 }
905 key = ra_scratch(as, allow);
906 emit_nm(as, A64I_CMPx, key, ra_allock(as, k, rset_exclude(allow, key)));
907 emit_lso(as, A64I_LDRx, key, idx, kofs);
908 if (bigofs)
909 emit_opk(as, A64I_ADDx, dest, node, ofs, RSET_GPR);
910}
911
912static void asm_uref(ASMState *as, IRIns *ir)
913{
914 Reg dest = ra_dest(as, ir, RSET_GPR);
915 if (irref_isk(ir->op1)) {
916 GCfunc *fn = ir_kfunc(IR(ir->op1));
917 MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
918 emit_lsptr(as, A64I_LDRx, dest, v);
919 } else {
920 Reg uv = ra_scratch(as, RSET_GPR);
921 Reg func = ra_alloc1(as, ir->op1, RSET_GPR);
922 if (ir->o == IR_UREFC) {
923 asm_guardcc(as, CC_NE);
924 emit_n(as, (A64I_CMPx^A64I_K12) | A64F_U12(1), RID_TMP);
925 emit_opk(as, A64I_ADDx, dest, uv,
926 (int32_t)offsetof(GCupval, tv), RSET_GPR);
927 emit_lso(as, A64I_LDRB, RID_TMP, uv, (int32_t)offsetof(GCupval, closed));
928 } else {
929 emit_lso(as, A64I_LDRx, dest, uv, (int32_t)offsetof(GCupval, v));
930 }
931 emit_lso(as, A64I_LDRx, uv, func,
932 (int32_t)offsetof(GCfuncL, uvptr) + 8*(int32_t)(ir->op2 >> 8));
933 }
934}
935
936static void asm_fref(ASMState *as, IRIns *ir)
937{
938 UNUSED(as); UNUSED(ir);
939 lua_assert(!ra_used(ir));
940}
941
942static void asm_strref(ASMState *as, IRIns *ir)
943{
944 RegSet allow = RSET_GPR;
945 Reg dest = ra_dest(as, ir, allow);
946 Reg base = ra_alloc1(as, ir->op1, allow);
947 IRIns *irr = IR(ir->op2);
948 int32_t ofs = sizeof(GCstr);
949 uint32_t m;
950 rset_clear(allow, base);
951 if (irref_isk(ir->op2) && (m = emit_isk12(ofs + irr->i))) {
952 emit_dn(as, A64I_ADDx^m, dest, base);
953 } else {
954 emit_dn(as, (A64I_ADDx^A64I_K12) | A64F_U12(ofs), dest, dest);
955 emit_dnm(as, A64I_ADDx, dest, base, ra_alloc1(as, ir->op2, allow));
956 }
957}
958
959/* -- Loads and stores ---------------------------------------------------- */
960
961static A64Ins asm_fxloadins(IRIns *ir)
962{
963 switch (irt_type(ir->t)) {
964 case IRT_I8: return A64I_LDRB ^ A64I_LS_S;
965 case IRT_U8: return A64I_LDRB;
966 case IRT_I16: return A64I_LDRH ^ A64I_LS_S;
967 case IRT_U16: return A64I_LDRH;
968 case IRT_NUM: return A64I_LDRd;
969 case IRT_FLOAT: return A64I_LDRs;
970 default: return irt_is64(ir->t) ? A64I_LDRx : A64I_LDRw;
971 }
972}
973
974static A64Ins asm_fxstoreins(IRIns *ir)
975{
976 switch (irt_type(ir->t)) {
977 case IRT_I8: case IRT_U8: return A64I_STRB;
978 case IRT_I16: case IRT_U16: return A64I_STRH;
979 case IRT_NUM: return A64I_STRd;
980 case IRT_FLOAT: return A64I_STRs;
981 default: return irt_is64(ir->t) ? A64I_STRx : A64I_STRw;
982 }
983}
984
985static void asm_fload(ASMState *as, IRIns *ir)
986{
987 Reg dest = ra_dest(as, ir, RSET_GPR);
988 Reg idx;
989 A64Ins ai = asm_fxloadins(ir);
990 int32_t ofs;
991 if (ir->op1 == REF_NIL) {
992 idx = RID_GL;
993 ofs = (ir->op2 << 2) - GG_OFS(g);
994 } else {
995 idx = ra_alloc1(as, ir->op1, RSET_GPR);
996 if (ir->op2 == IRFL_TAB_ARRAY) {
997 ofs = asm_fuseabase(as, ir->op1);
998 if (ofs) { /* Turn the t->array load into an add for colocated arrays. */
999 emit_dn(as, (A64I_ADDx^A64I_K12) | A64F_U12(ofs), dest, idx);
1000 return;
1001 }
1002 }
1003 ofs = field_ofs[ir->op2];
1004 }
1005 emit_lso(as, ai, (dest & 31), idx, ofs);
1006}
1007
1008static void asm_fstore(ASMState *as, IRIns *ir)
1009{
1010 if (ir->r != RID_SINK) {
1011 Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
1012 IRIns *irf = IR(ir->op1);
1013 Reg idx = ra_alloc1(as, irf->op1, rset_exclude(RSET_GPR, src));
1014 int32_t ofs = field_ofs[irf->op2];
1015 emit_lso(as, asm_fxstoreins(ir), (src & 31), idx, ofs);
1016 }
1017}
1018
1019static void asm_xload(ASMState *as, IRIns *ir)
1020{
1021 Reg dest = ra_dest(as, ir, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
1022 lua_assert(!(ir->op2 & IRXLOAD_UNALIGNED));
1023 asm_fusexref(as, asm_fxloadins(ir), dest, ir->op1, RSET_GPR);
1024}
1025
1026static void asm_xstore(ASMState *as, IRIns *ir)
1027{
1028 if (ir->r != RID_SINK) {
1029 Reg src = ra_alloc1(as, ir->op2, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
1030 asm_fusexref(as, asm_fxstoreins(ir), src, ir->op1,
1031 rset_exclude(RSET_GPR, src));
1032 }
1033}
1034
1035static void asm_ahuvload(ASMState *as, IRIns *ir)
1036{
1037 Reg idx, tmp, type;
1038 int32_t ofs = 0;
1039 RegSet gpr = RSET_GPR, allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR;
1040 lua_assert(irt_isnum(ir->t) || irt_ispri(ir->t) || irt_isaddr(ir->t) ||
1041 irt_isint(ir->t));
1042 if (ra_used(ir)) {
1043 Reg dest = ra_dest(as, ir, allow);
1044 tmp = irt_isnum(ir->t) ? ra_scratch(as, rset_clear(gpr, dest)) : dest;
1045 if (irt_isaddr(ir->t)) {
1046 emit_dn(as, A64I_ANDx^emit_isk13(LJ_GCVMASK, 1), dest, dest);
1047 } else if (irt_isnum(ir->t)) {
1048 emit_dn(as, A64I_FMOV_D_R, (dest & 31), tmp);
1049 } else if (irt_isint(ir->t)) {
1050 emit_dm(as, A64I_MOVw, dest, dest);
1051 }
1052 } else {
1053 tmp = ra_scratch(as, gpr);
1054 }
1055 type = ra_scratch(as, rset_clear(gpr, tmp));
1056 idx = asm_fuseahuref(as, ir->op1, &ofs, rset_clear(gpr, type), A64I_LDRx);
1057 /* Always do the type check, even if the load result is unused. */
1058 asm_guardcc(as, irt_isnum(ir->t) ? CC_LS : CC_NE);
1059 if (irt_type(ir->t) >= IRT_NUM) {
1060 lua_assert(irt_isinteger(ir->t) || irt_isnum(ir->t));
1061 emit_nm(as, A64I_CMPx | A64F_SH(A64SH_LSR, 32),
1062 ra_allock(as, LJ_TISNUM << 15, rset_exclude(gpr, idx)), tmp);
1063 } else if (irt_isaddr(ir->t)) {
1064 emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(-irt_toitype(ir->t)), type);
1065 emit_dn(as, A64I_ASRx | A64F_IMMR(47), type, tmp);
1066 } else if (irt_isnil(ir->t)) {
1067 emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(1), tmp);
1068 } else {
1069 emit_nm(as, A64I_CMPx | A64F_SH(A64SH_LSR, 32),
1070 ra_allock(as, (irt_toitype(ir->t) << 15) | 0x7fff, allow), tmp);
1071 }
1072 if (ofs & FUSE_REG)
1073 emit_dnm(as, (A64I_LDRx^A64I_LS_R)|A64I_LS_UXTWx|A64I_LS_SH, tmp, idx, (ofs & 31));
1074 else
1075 emit_lso(as, A64I_LDRx, tmp, idx, ofs);
1076}
1077
1078static void asm_ahustore(ASMState *as, IRIns *ir)
1079{
1080 if (ir->r != RID_SINK) {
1081 RegSet allow = RSET_GPR;
1082 Reg idx, src = RID_NONE, tmp = RID_TMP, type = RID_NONE;
1083 int32_t ofs = 0;
1084 if (irt_isnum(ir->t)) {
1085 src = ra_alloc1(as, ir->op2, RSET_FPR);
1086 idx = asm_fuseahuref(as, ir->op1, &ofs, allow, A64I_STRd);
1087 if (ofs & FUSE_REG)
1088 emit_dnm(as, (A64I_STRd^A64I_LS_R)|A64I_LS_UXTWx|A64I_LS_SH, (src & 31), idx, (ofs &31));
1089 else
1090 emit_lso(as, A64I_STRd, (src & 31), idx, ofs);
1091 } else {
1092 if (!irt_ispri(ir->t)) {
1093 src = ra_alloc1(as, ir->op2, allow);
1094 rset_clear(allow, src);
1095 if (irt_isinteger(ir->t))
1096 type = ra_allock(as, (uint64_t)(int32_t)LJ_TISNUM << 47, allow);
1097 else
1098 type = ra_allock(as, irt_toitype(ir->t), allow);
1099 } else {
1100 tmp = type = ra_allock(as, ~((int64_t)~irt_toitype(ir->t)<<47), allow);
1101 }
1102 idx = asm_fuseahuref(as, ir->op1, &ofs, rset_exclude(allow, type),
1103 A64I_STRx);
1104 if (ofs & FUSE_REG)
1105 emit_dnm(as, (A64I_STRx^A64I_LS_R)|A64I_LS_UXTWx|A64I_LS_SH, tmp, idx, (ofs & 31));
1106 else
1107 emit_lso(as, A64I_STRx, tmp, idx, ofs);
1108 if (ra_hasreg(src)) {
1109 if (irt_isinteger(ir->t)) {
1110 emit_dnm(as, A64I_ADDx | A64F_EX(A64EX_UXTW), tmp, type, src);
1111 } else {
1112 emit_dnm(as, A64I_ADDx | A64F_SH(A64SH_LSL, 47), tmp, src, type);
1113 }
1114 }
1115 }
1116 }
1117}
1118
1119static void asm_sload(ASMState *as, IRIns *ir)
1120{
1121 int32_t ofs = 8*((int32_t)ir->op1-2);
1122 IRType1 t = ir->t;
1123 Reg dest = RID_NONE, base;
1124 RegSet allow = RSET_GPR;
1125 lua_assert(!(ir->op2 & IRSLOAD_PARENT)); /* Handled by asm_head_side(). */
1126 lua_assert(irt_isguard(t) || !(ir->op2 & IRSLOAD_TYPECHECK));
1127 if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
1128 dest = ra_scratch(as, RSET_FPR);
1129 asm_tointg(as, ir, dest);
1130 t.irt = IRT_NUM; /* Continue with a regular number type check. */
1131 } else if (ra_used(ir)) {
1132 Reg tmp = RID_NONE;
1133 if ((ir->op2 & IRSLOAD_CONVERT))
1134 tmp = ra_scratch(as, irt_isint(t) ? RSET_FPR : RSET_GPR);
1135 lua_assert((irt_isnum(t)) || irt_isint(t) || irt_isaddr(t));
1136 dest = ra_dest(as, ir, irt_isnum(t) ? RSET_FPR : allow);
1137 base = ra_alloc1(as, REF_BASE, rset_clear(allow, dest));
1138 if (irt_isaddr(t)) {
1139 emit_dn(as, A64I_ANDx^emit_isk13(LJ_GCVMASK, 1), dest, dest);
1140 } else if ((ir->op2 & IRSLOAD_CONVERT)) {
1141 if (irt_isint(t)) {
1142 emit_dn(as, A64I_FCVT_S32_F64, dest, (tmp & 31));
1143 /* If value is already loaded for type check, move it to FPR. */
1144 if ((ir->op2 & IRSLOAD_TYPECHECK))
1145 emit_dn(as, A64I_FMOV_D_R, (tmp & 31), dest);
1146 else
1147 dest = tmp;
1148 t.irt = IRT_NUM; /* Check for original type. */
1149 } else {
1150 emit_dn(as, A64I_FCVT_F64_S32, (dest & 31), tmp);
1151 dest = tmp;
1152 t.irt = IRT_INT; /* Check for original type. */
1153 }
1154 } else if (irt_isint(t) && (ir->op2 & IRSLOAD_TYPECHECK)) {
1155 emit_dm(as, A64I_MOVw, dest, dest);
1156 }
1157 goto dotypecheck;
1158 }
1159 base = ra_alloc1(as, REF_BASE, allow);
1160dotypecheck:
1161 rset_clear(allow, base);
1162 if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1163 Reg tmp;
1164 if (ra_hasreg(dest) && rset_test(RSET_GPR, dest)) {
1165 tmp = dest;
1166 } else {
1167 tmp = ra_scratch(as, allow);
1168 rset_clear(allow, tmp);
1169 }
1170 if (irt_isnum(t) && !(ir->op2 & IRSLOAD_CONVERT))
1171 emit_dn(as, A64I_FMOV_D_R, (dest & 31), tmp);
1172 /* Need type check, even if the load result is unused. */
1173 asm_guardcc(as, irt_isnum(t) ? CC_LS : CC_NE);
1174 if (irt_type(t) >= IRT_NUM) {
1175 lua_assert(irt_isinteger(t) || irt_isnum(t));
1176 emit_nm(as, A64I_CMPx | A64F_SH(A64SH_LSR, 32),
1177 ra_allock(as, LJ_TISNUM << 15, allow), tmp);
1178 } else if (irt_isnil(t)) {
1179 emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(1), tmp);
1180 } else if (irt_ispri(t)) {
1181 emit_nm(as, A64I_CMPx,
1182 ra_allock(as, ~((int64_t)~irt_toitype(t) << 47) , allow), tmp);
1183 } else {
1184 Reg type = ra_scratch(as, allow);
1185 emit_n(as, (A64I_CMNx^A64I_K12) | A64F_U12(-irt_toitype(t)), type);
1186 emit_dn(as, A64I_ASRx | A64F_IMMR(47), type, tmp);
1187 }
1188 emit_lso(as, A64I_LDRx, tmp, base, ofs);
1189 return;
1190 }
1191 if (ra_hasreg(dest)) {
1192 emit_lso(as, irt_isnum(t) ? A64I_LDRd :
1193 (irt_isint(t) ? A64I_LDRw : A64I_LDRx), (dest & 31), base,
1194 ofs ^ ((LJ_BE && irt_isint(t) ? 4 : 0)));
1195 }
1196}
1197
1198/* -- Allocations --------------------------------------------------------- */
1199
1200#if LJ_HASFFI
1201static void asm_cnew(ASMState *as, IRIns *ir)
1202{
1203 CTState *cts = ctype_ctsG(J2G(as->J));
1204 CTypeID id = (CTypeID)IR(ir->op1)->i;
1205 CTSize sz;
1206 CTInfo info = lj_ctype_info(cts, id, &sz);
1207 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1208 IRRef args[4];
1209 RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1210 lua_assert(sz != CTSIZE_INVALID || (ir->o == IR_CNEW && ir->op2 != REF_NIL));
1211
1212 as->gcsteps++;
1213 asm_setupresult(as, ir, ci); /* GCcdata * */
1214 /* Initialize immutable cdata object. */
1215 if (ir->o == IR_CNEWI) {
1216 int32_t ofs = sizeof(GCcdata);
1217 Reg r = ra_alloc1(as, ir->op2, allow);
1218 lua_assert(sz == 4 || sz == 8);
1219 emit_lso(as, sz == 8 ? A64I_STRx : A64I_STRw, r, RID_RET, ofs);
1220 } else if (ir->op2 != REF_NIL) { /* Create VLA/VLS/aligned cdata. */
1221 ci = &lj_ir_callinfo[IRCALL_lj_cdata_newv];
1222 args[0] = ASMREF_L; /* lua_State *L */
1223 args[1] = ir->op1; /* CTypeID id */
1224 args[2] = ir->op2; /* CTSize sz */
1225 args[3] = ASMREF_TMP1; /* CTSize align */
1226 asm_gencall(as, ci, args);
1227 emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)ctype_align(info));
1228 return;
1229 }
1230
1231 /* Initialize gct and ctypeid. lj_mem_newgco() already sets marked. */
1232 {
1233 Reg r = (id < 65536) ? RID_X1 : ra_allock(as, id, allow);
1234 emit_lso(as, A64I_STRB, RID_TMP, RID_RET, offsetof(GCcdata, gct));
1235 emit_lso(as, A64I_STRH, r, RID_RET, offsetof(GCcdata, ctypeid));
1236 emit_d(as, A64I_MOVZw | A64F_U16(~LJ_TCDATA), RID_TMP);
1237 if (id < 65536) emit_d(as, A64I_MOVZw | A64F_U16(id), RID_X1);
1238 }
1239 args[0] = ASMREF_L; /* lua_State *L */
1240 args[1] = ASMREF_TMP1; /* MSize size */
1241 asm_gencall(as, ci, args);
1242 ra_allockreg(as, (int32_t)(sz+sizeof(GCcdata)),
1243 ra_releasetmp(as, ASMREF_TMP1));
1244}
1245#else
1246#define asm_cnew(as, ir) ((void)0)
1247#endif
1248
1249/* -- Write barriers ------------------------------------------------------ */
1250
1251static void asm_tbar(ASMState *as, IRIns *ir)
1252{
1253 Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1254 Reg link = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1255 Reg gr = ra_allock(as, i64ptr(J2G(as->J)),
1256 rset_exclude(rset_exclude(RSET_GPR, tab), link));
1257 Reg mark = RID_TMP;
1258 MCLabel l_end = emit_label(as);
1259 emit_lso(as, A64I_STRx, link, tab, (int32_t)offsetof(GCtab, gclist));
1260 emit_lso(as, A64I_STRB, mark, tab, (int32_t)offsetof(GCtab, marked));
1261 emit_lso(as, A64I_STRx, tab, gr,
1262 (int32_t)offsetof(global_State, gc.grayagain));
1263 emit_dn(as, A64I_ANDw^emit_isk13(~LJ_GC_BLACK, 0), mark, mark);
1264 emit_lso(as, A64I_LDRx, link, gr,
1265 (int32_t)offsetof(global_State, gc.grayagain));
1266 emit_cond_branch(as, CC_EQ, l_end);
1267 emit_n(as, A64I_TSTw^emit_isk13(LJ_GC_BLACK, 0), mark);
1268 emit_lso(as, A64I_LDRB, mark, tab, (int32_t)offsetof(GCtab, marked));
1269}
1270
1271static void asm_obar(ASMState *as, IRIns *ir)
1272{
1273 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1274 IRRef args[2];
1275 MCLabel l_end;
1276 RegSet allow = RSET_GPR;
1277 Reg obj, val, tmp;
1278 /* No need for other object barriers (yet). */
1279 lua_assert(IR(ir->op1)->o == IR_UREFC);
1280 ra_evictset(as, RSET_SCRATCH);
1281 l_end = emit_label(as);
1282 args[0] = ASMREF_TMP1; /* global_State *g */
1283 args[1] = ir->op1; /* TValue *tv */
1284 asm_gencall(as, ci, args);
1285 ra_allockreg(as, i64ptr(J2G(as->J)), ra_releasetmp(as, ASMREF_TMP1) );
1286 obj = IR(ir->op1)->r;
1287 tmp = ra_scratch(as, rset_exclude(allow, obj));
1288 emit_cond_branch(as, CC_EQ, l_end);
1289 emit_n(as, A64I_TSTw^emit_isk13(LJ_GC_BLACK, 0), tmp);
1290 emit_cond_branch(as, CC_EQ, l_end);
1291 emit_n(as, A64I_TSTw^emit_isk13(LJ_GC_WHITES, 0), RID_TMP);
1292 val = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, obj));
1293 emit_lso(as, A64I_LDRB, tmp, obj,
1294 (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1295 emit_lso(as, A64I_LDRB, RID_TMP, val, (int32_t)offsetof(GChead, marked));
1296}
1297
1298/* -- Arithmetic and logic operations ------------------------------------- */
1299
1300static void asm_fparith(ASMState *as, IRIns *ir, A64Ins ai)
1301{
1302 Reg dest = ra_dest(as, ir, RSET_FPR);
1303 Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1304 right = (left >> 8); left &= 255;
1305 emit_dnm(as, ai, (dest & 31), (left & 31), (right & 31));
1306}
1307
1308static void asm_fpunary(ASMState *as, IRIns *ir, A64Ins ai)
1309{
1310 Reg dest = ra_dest(as, ir, RSET_FPR);
1311 Reg left = ra_hintalloc(as, ir->op1, dest, RSET_FPR);
1312 emit_dn(as, ai, (dest & 31), (left & 31));
1313}
1314
1315static void asm_fpmath(ASMState *as, IRIns *ir)
1316{
1317 IRFPMathOp fpm = (IRFPMathOp)ir->op2;
1318 if (fpm == IRFPM_SQRT) {
1319 asm_fpunary(as, ir, A64I_FSQRTd);
1320 } else if (fpm <= IRFPM_TRUNC) {
1321 asm_fpunary(as, ir, fpm == IRFPM_FLOOR ? A64I_FRINTMd :
1322 fpm == IRFPM_CEIL ? A64I_FRINTPd : A64I_FRINTZd);
1323 } else if (fpm == IRFPM_EXP2 && asm_fpjoin_pow(as, ir)) {
1324 return;
1325 } else {
1326 asm_callid(as, ir, IRCALL_lj_vm_floor + fpm);
1327 }
1328}
1329
1330static int asm_swapops(ASMState *as, IRRef lref, IRRef rref)
1331{
1332 IRIns *ir;
1333 if (irref_isk(rref))
1334 return 0; /* Don't swap constants to the left. */
1335 if (irref_isk(lref))
1336 return 1; /* But swap constants to the right. */
1337 ir = IR(rref);
1338 if ((ir->o >= IR_BSHL && ir->o <= IR_BSAR) ||
1339 (ir->o == IR_ADD && ir->op1 == ir->op2) ||
1340 (ir->o == IR_CONV && ir->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT)))
1341 return 0; /* Don't swap fusable operands to the left. */
1342 ir = IR(lref);
1343 if ((ir->o >= IR_BSHL && ir->o <= IR_BSAR) ||
1344 (ir->o == IR_ADD && ir->op1 == ir->op2) ||
1345 (ir->o == IR_CONV && ir->op2 == ((IRT_I64<<IRCONV_DSH)|IRT_INT|IRCONV_SEXT)))
1346 return 1; /* But swap fusable operands to the right. */
1347 return 0; /* Otherwise don't swap. */
1348}
1349
1350static void asm_intop(ASMState *as, IRIns *ir, A64Ins ai)
1351{
1352 IRRef lref = ir->op1, rref = ir->op2;
1353 Reg left, dest = ra_dest(as, ir, RSET_GPR);
1354 uint32_t m;
1355 if ((ai & ~A64I_S) != A64I_SUBw && asm_swapops(as, lref, rref)) {
1356 IRRef tmp = lref; lref = rref; rref = tmp;
1357 }
1358 left = ra_hintalloc(as, lref, dest, RSET_GPR);
1359 if (irt_is64(ir->t)) ai |= A64I_X;
1360 m = asm_fuseopm(as, ai, rref, rset_exclude(RSET_GPR, left));
1361 if (irt_isguard(ir->t)) { /* For IR_ADDOV etc. */
1362 asm_guardcc(as, CC_VS);
1363 ai |= A64I_S;
1364 }
1365 emit_dn(as, ai^m, dest, left);
1366}
1367
1368static void asm_intop_s(ASMState *as, IRIns *ir, A64Ins ai)
1369{
1370 if (as->flagmcp == as->mcp) { /* Drop cmp r, #0. */
1371 as->flagmcp = NULL;
1372 as->mcp++;
1373 ai |= A64I_S;
1374 }
1375 asm_intop(as, ir, ai);
1376}
1377
1378static void asm_intneg(ASMState *as, IRIns *ir)
1379{
1380 Reg dest = ra_dest(as, ir, RSET_GPR);
1381 Reg left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1382 emit_dm(as, irt_is64(ir->t) ? A64I_NEGx : A64I_NEGw, dest, left);
1383}
1384
1385/* NYI: use add/shift for MUL(OV) with constants. FOLD only does 2^k. */
1386static void asm_intmul(ASMState *as, IRIns *ir)
1387{
1388 Reg dest = ra_dest(as, ir, RSET_GPR);
1389 Reg left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, dest));
1390 Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1391 if (irt_isguard(ir->t)) { /* IR_MULOV */
1392 asm_guardcc(as, CC_NE);
1393 emit_dm(as, A64I_MOVw, dest, dest); /* Zero-extend. */
1394 emit_nm(as, A64I_CMPw | A64F_SH(A64SH_ASR, 31), RID_TMP, dest);
1395 emit_dn(as, A64I_ASRx | A64F_IMMR(32), RID_TMP, dest);
1396 emit_dnm(as, A64I_SMULL, dest, right, left);
1397 } else {
1398 emit_dnm(as, irt_is64(ir->t) ? A64I_MULx : A64I_MULw, dest, left, right);
1399 }
1400}
1401
1402static void asm_add(ASMState *as, IRIns *ir)
1403{
1404 if (irt_isnum(ir->t)) {
1405 if (!asm_fusemadd(as, ir, A64I_FMADDd, A64I_FMADDd))
1406 asm_fparith(as, ir, A64I_FADDd);
1407 return;
1408 }
1409 asm_intop_s(as, ir, A64I_ADDw);
1410}
1411
1412static void asm_sub(ASMState *as, IRIns *ir)
1413{
1414 if (irt_isnum(ir->t)) {
1415 if (!asm_fusemadd(as, ir, A64I_FNMSUBd, A64I_FMSUBd))
1416 asm_fparith(as, ir, A64I_FSUBd);
1417 return;
1418 }
1419 asm_intop_s(as, ir, A64I_SUBw);
1420}
1421
1422static void asm_mul(ASMState *as, IRIns *ir)
1423{
1424 if (irt_isnum(ir->t)) {
1425 asm_fparith(as, ir, A64I_FMULd);
1426 return;
1427 }
1428 asm_intmul(as, ir);
1429}
1430
1431static void asm_div(ASMState *as, IRIns *ir)
1432{
1433#if LJ_HASFFI
1434 if (!irt_isnum(ir->t))
1435 asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_divi64 :
1436 IRCALL_lj_carith_divu64);
1437 else
1438#endif
1439 asm_fparith(as, ir, A64I_FDIVd);
1440}
1441
1442static void asm_pow(ASMState *as, IRIns *ir)
1443{
1444#if LJ_HASFFI
1445 if (!irt_isnum(ir->t))
1446 asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_powi64 :
1447 IRCALL_lj_carith_powu64);
1448 else
1449#endif
1450 asm_callid(as, ir, IRCALL_lj_vm_powi);
1451}
1452
1453#define asm_addov(as, ir) asm_add(as, ir)
1454#define asm_subov(as, ir) asm_sub(as, ir)
1455#define asm_mulov(as, ir) asm_mul(as, ir)
1456
1457#define asm_abs(as, ir) asm_fpunary(as, ir, A64I_FABS)
1458#define asm_atan2(as, ir) asm_callid(as, ir, IRCALL_atan2)
1459#define asm_ldexp(as, ir) asm_callid(as, ir, IRCALL_ldexp)
1460
1461static void asm_mod(ASMState *as, IRIns *ir)
1462{
1463#if LJ_HASFFI
1464 if (!irt_isint(ir->t))
1465 asm_callid(as, ir, irt_isi64(ir->t) ? IRCALL_lj_carith_modi64 :
1466 IRCALL_lj_carith_modu64);
1467 else
1468#endif
1469 asm_callid(as, ir, IRCALL_lj_vm_modi);
1470}
1471
1472static void asm_neg(ASMState *as, IRIns *ir)
1473{
1474 if (irt_isnum(ir->t)) {
1475 asm_fpunary(as, ir, A64I_FNEGd);
1476 return;
1477 }
1478 asm_intneg(as, ir);
1479}
1480
1481static void asm_band(ASMState *as, IRIns *ir)
1482{
1483 A64Ins ai = A64I_ANDw;
1484 if (asm_fuseandshift(as, ir))
1485 return;
1486 if (as->flagmcp == as->mcp) {
1487 /* Try to drop cmp r, #0. */
1488 as->flagmcp = NULL;
1489 as->mcp++;
1490 ai = A64I_ANDSw;
1491 }
1492 asm_intop(as, ir, ai);
1493}
1494
1495static void asm_borbxor(ASMState *as, IRIns *ir, A64Ins ai)
1496{
1497 IRRef lref = ir->op1, rref = ir->op2;
1498 IRIns *irl = IR(lref), *irr = IR(rref);
1499 if ((canfuse(as, irl) && irl->o == IR_BNOT && !irref_isk(rref)) ||
1500 (canfuse(as, irr) && irr->o == IR_BNOT && !irref_isk(lref))) {
1501 Reg left, dest = ra_dest(as, ir, RSET_GPR);
1502 uint32_t m;
1503 if (irl->o == IR_BNOT) {
1504 IRRef tmp = lref; lref = rref; rref = tmp;
1505 }
1506 left = ra_alloc1(as, lref, RSET_GPR);
1507 ai |= A64I_ON;
1508 if (irt_is64(ir->t)) ai |= A64I_X;
1509 m = asm_fuseopm(as, ai, IR(rref)->op1, rset_exclude(RSET_GPR, left));
1510 emit_dn(as, ai^m, dest, left);
1511 } else {
1512 asm_intop(as, ir, ai);
1513 }
1514}
1515
1516static void asm_bor(ASMState *as, IRIns *ir)
1517{
1518 if (asm_fuseorshift(as, ir))
1519 return;
1520 asm_borbxor(as, ir, A64I_ORRw);
1521}
1522
1523#define asm_bxor(as, ir) asm_borbxor(as, ir, A64I_EORw)
1524
1525static void asm_bnot(ASMState *as, IRIns *ir)
1526{
1527 A64Ins ai = A64I_MVNw;
1528 Reg dest = ra_dest(as, ir, RSET_GPR);
1529 uint32_t m = asm_fuseopm(as, ai, ir->op1, RSET_GPR);
1530 if (irt_is64(ir->t)) ai |= A64I_X;
1531 emit_d(as, ai^m, dest);
1532}
1533
1534static void asm_bswap(ASMState *as, IRIns *ir)
1535{
1536 Reg dest = ra_dest(as, ir, RSET_GPR);
1537 Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1538 emit_dn(as, irt_is64(ir->t) ? A64I_REVx : A64I_REVw, dest, left);
1539}
1540
1541static void asm_bitshift(ASMState *as, IRIns *ir, A64Ins ai, A64Shift sh)
1542{
1543 int32_t shmask = irt_is64(ir->t) ? 63 : 31;
1544 if (irref_isk(ir->op2)) { /* Constant shifts. */
1545 Reg left, dest = ra_dest(as, ir, RSET_GPR);
1546 int32_t shift = (IR(ir->op2)->i & shmask);
1547 IRIns *irl = IR(ir->op1);
1548 if (shmask == 63) ai += A64I_UBFMx - A64I_UBFMw;
1549
1550 /* Fuse BSHL + BSHR/BSAR into UBFM/SBFM aka UBFX/SBFX/UBFIZ/SBFIZ. */
1551 if ((sh == A64SH_LSR || sh == A64SH_ASR) && canfuse(as, irl)) {
1552 if (irl->o == IR_BSHL && irref_isk(irl->op2)) {
1553 int32_t shift2 = (IR(irl->op2)->i & shmask);
1554 shift = ((shift - shift2) & shmask);
1555 shmask -= shift2;
1556 ir = irl;
1557 }
1558 }
1559
1560 left = ra_alloc1(as, ir->op1, RSET_GPR);
1561 switch (sh) {
1562 case A64SH_LSL:
1563 emit_dn(as, ai | A64F_IMMS(shmask-shift) |
1564 A64F_IMMR((shmask-shift+1)&shmask), dest, left);
1565 break;
1566 case A64SH_LSR: case A64SH_ASR:
1567 emit_dn(as, ai | A64F_IMMS(shmask) | A64F_IMMR(shift), dest, left);
1568 break;
1569 case A64SH_ROR:
1570 emit_dnm(as, ai | A64F_IMMS(shift), dest, left, left);
1571 break;
1572 }
1573 } else { /* Variable-length shifts. */
1574 Reg dest = ra_dest(as, ir, RSET_GPR);
1575 Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1576 Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1577 emit_dnm(as, (shmask == 63 ? A64I_SHRx : A64I_SHRw) | A64F_BSH(sh), dest, left, right);
1578 }
1579}
1580
1581#define asm_bshl(as, ir) asm_bitshift(as, ir, A64I_UBFMw, A64SH_LSL)
1582#define asm_bshr(as, ir) asm_bitshift(as, ir, A64I_UBFMw, A64SH_LSR)
1583#define asm_bsar(as, ir) asm_bitshift(as, ir, A64I_SBFMw, A64SH_ASR)
1584#define asm_bror(as, ir) asm_bitshift(as, ir, A64I_EXTRw, A64SH_ROR)
1585#define asm_brol(as, ir) lua_assert(0)
1586
1587static void asm_intmin_max(ASMState *as, IRIns *ir, A64CC cc)
1588{
1589 Reg dest = ra_dest(as, ir, RSET_GPR);
1590 Reg left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1591 Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1592 emit_dnm(as, A64I_CSELw|A64F_CC(cc), dest, left, right);
1593 emit_nm(as, A64I_CMPw, left, right);
1594}
1595
1596static void asm_fpmin_max(ASMState *as, IRIns *ir, A64CC fcc)
1597{
1598 Reg dest = (ra_dest(as, ir, RSET_FPR) & 31);
1599 Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1600 right = ((left >> 8) & 31); left &= 31;
1601 emit_dnm(as, A64I_FCSELd | A64F_CC(fcc), dest, left, right);
1602 emit_nm(as, A64I_FCMPd, left, right);
1603}
1604
1605static void asm_min_max(ASMState *as, IRIns *ir, A64CC cc, A64CC fcc)
1606{
1607 if (irt_isnum(ir->t))
1608 asm_fpmin_max(as, ir, fcc);
1609 else
1610 asm_intmin_max(as, ir, cc);
1611}
1612
1613#define asm_max(as, ir) asm_min_max(as, ir, CC_GT, CC_HI)
1614#define asm_min(as, ir) asm_min_max(as, ir, CC_LT, CC_LO)
1615
1616/* -- Comparisons --------------------------------------------------------- */
1617
1618/* Map of comparisons to flags. ORDER IR. */
1619static const uint8_t asm_compmap[IR_ABC+1] = {
1620 /* op FP swp int cc FP cc */
1621 /* LT */ CC_GE + (CC_HS << 4),
1622 /* GE x */ CC_LT + (CC_HI << 4),
1623 /* LE */ CC_GT + (CC_HI << 4),
1624 /* GT x */ CC_LE + (CC_HS << 4),
1625 /* ULT x */ CC_HS + (CC_LS << 4),
1626 /* UGE */ CC_LO + (CC_LO << 4),
1627 /* ULE x */ CC_HI + (CC_LO << 4),
1628 /* UGT */ CC_LS + (CC_LS << 4),
1629 /* EQ */ CC_NE + (CC_NE << 4),
1630 /* NE */ CC_EQ + (CC_EQ << 4),
1631 /* ABC */ CC_LS + (CC_LS << 4) /* Same as UGT. */
1632};
1633
1634/* FP comparisons. */
1635static void asm_fpcomp(ASMState *as, IRIns *ir)
1636{
1637 Reg left, right;
1638 A64Ins ai;
1639 int swp = ((ir->o ^ (ir->o >> 2)) & ~(ir->o >> 3) & 1);
1640 if (!swp && irref_isk(ir->op2) && ir_knum(IR(ir->op2))->u64 == 0) {
1641 left = (ra_alloc1(as, ir->op1, RSET_FPR) & 31);
1642 right = 0;
1643 ai = A64I_FCMPZd;
1644 } else {
1645 left = ra_alloc2(as, ir, RSET_FPR);
1646 if (swp) {
1647 right = (left & 31); left = ((left >> 8) & 31);
1648 } else {
1649 right = ((left >> 8) & 31); left &= 31;
1650 }
1651 ai = A64I_FCMPd;
1652 }
1653 asm_guardcc(as, (asm_compmap[ir->o] >> 4));
1654 emit_nm(as, ai, left, right);
1655}
1656
1657/* Integer comparisons. */
1658static void asm_intcomp(ASMState *as, IRIns *ir)
1659{
1660 A64CC oldcc, cc = (asm_compmap[ir->o] & 15);
1661 A64Ins ai = irt_is64(ir->t) ? A64I_CMPx : A64I_CMPw;
1662 IRRef lref = ir->op1, rref = ir->op2;
1663 Reg left;
1664 uint32_t m;
1665 int cmpprev0 = 0;
1666 lua_assert(irt_is64(ir->t) || irt_isint(ir->t) ||
1667 irt_isu32(ir->t) || irt_isaddr(ir->t) || irt_isu8(ir->t));
1668 if (asm_swapops(as, lref, rref)) {
1669 IRRef tmp = lref; lref = rref; rref = tmp;
1670 if (cc >= CC_GE) cc ^= 7; /* LT <-> GT, LE <-> GE */
1671 else if (cc > CC_NE) cc ^= 11; /* LO <-> HI, LS <-> HS */
1672 }
1673 oldcc = cc;
1674 if (irref_isk(rref) && get_k64val(IR(rref)) == 0) {
1675 IRIns *irl = IR(lref);
1676 if (cc == CC_GE) cc = CC_PL;
1677 else if (cc == CC_LT) cc = CC_MI;
1678 else if (cc > CC_NE) goto nocombine; /* Other conds don't work with tst. */
1679 cmpprev0 = (irl+1 == ir);
1680 /* Combine and-cmp-bcc into tbz/tbnz or and-cmp into tst. */
1681 if (cmpprev0 && irl->o == IR_BAND && !ra_used(irl)) {
1682 IRRef blref = irl->op1, brref = irl->op2;
1683 uint32_t m2 = 0;
1684 Reg bleft;
1685 if (asm_swapops(as, blref, brref)) {
1686 Reg tmp = blref; blref = brref; brref = tmp;
1687 }
1688 if (irref_isk(brref)) {
1689 uint64_t k = get_k64val(IR(brref));
1690 if (k && !(k & (k-1)) && (cc == CC_EQ || cc == CC_NE)) {
1691 asm_guardtnb(as, cc == CC_EQ ? A64I_TBZ : A64I_TBNZ,
1692 ra_alloc1(as, blref, RSET_GPR), emit_ctz64(k));
1693 return;
1694 }
1695 m2 = emit_isk13(k, irt_is64(irl->t));
1696 }
1697 bleft = ra_alloc1(as, blref, RSET_GPR);
1698 ai = (irt_is64(irl->t) ? A64I_TSTx : A64I_TSTw);
1699 if (!m2)
1700 m2 = asm_fuseopm(as, ai, brref, rset_exclude(RSET_GPR, bleft));
1701 asm_guardcc(as, cc);
1702 emit_n(as, ai^m2, bleft);
1703 return;
1704 }
1705 if (cc == CC_EQ || cc == CC_NE) {
1706 /* Combine cmp-bcc into cbz/cbnz. */
1707 ai = cc == CC_EQ ? A64I_CBZ : A64I_CBNZ;
1708 if (irt_is64(ir->t)) ai |= A64I_X;
1709 asm_guardcnb(as, ai, ra_alloc1(as, lref, RSET_GPR));
1710 return;
1711 }
1712 }
1713nocombine:
1714 left = ra_alloc1(as, lref, RSET_GPR);
1715 m = asm_fuseopm(as, ai, rref, rset_exclude(RSET_GPR, left));
1716 asm_guardcc(as, cc);
1717 emit_n(as, ai^m, left);
1718 /* Signed comparison with zero and referencing previous ins? */
1719 if (cmpprev0 && (oldcc <= CC_NE || oldcc >= CC_GE))
1720 as->flagmcp = as->mcp; /* Allow elimination of the compare. */
1721}
1722
1723static void asm_comp(ASMState *as, IRIns *ir)
1724{
1725 if (irt_isnum(ir->t))
1726 asm_fpcomp(as, ir);
1727 else
1728 asm_intcomp(as, ir);
1729}
1730
1731#define asm_equal(as, ir) asm_comp(as, ir)
1732
1733/* -- Support for 64 bit ops in 32 bit mode ------------------------------- */
1734
1735/* Hiword op of a split 64 bit op. Previous op must be the loword op. */
1736static void asm_hiop(ASMState *as, IRIns *ir)
1737{
1738 UNUSED(as); UNUSED(ir); lua_assert(0); /* Unused on 64 bit. */
1739}
1740
1741/* -- Profiling ----------------------------------------------------------- */
1742
1743static void asm_prof(ASMState *as, IRIns *ir)
1744{
1745 uint32_t k = emit_isk13(HOOK_PROFILE, 0);
1746 lua_assert(k != 0);
1747 UNUSED(ir);
1748 asm_guardcc(as, CC_NE);
1749 emit_n(as, A64I_TSTw^k, RID_TMP);
1750 emit_lsptr(as, A64I_LDRB, RID_TMP, (void *)&J2G(as->J)->hookmask);
1751}
1752
1753/* -- Stack handling ------------------------------------------------------ */
1754
1755/* Check Lua stack size for overflow. Use exit handler as fallback. */
1756static void asm_stack_check(ASMState *as, BCReg topslot,
1757 IRIns *irp, RegSet allow, ExitNo exitno)
1758{
1759 Reg pbase;
1760 uint32_t k;
1761 if (irp) {
1762 if (!ra_hasspill(irp->s)) {
1763 pbase = irp->r;
1764 lua_assert(ra_hasreg(pbase));
1765 } else if (allow) {
1766 pbase = rset_pickbot(allow);
1767 } else {
1768 pbase = RID_RET;
1769 emit_lso(as, A64I_LDRx, RID_RET, RID_SP, 0); /* Restore temp register. */
1770 }
1771 } else {
1772 pbase = RID_BASE;
1773 }
1774 emit_cond_branch(as, CC_LS, asm_exitstub_addr(as, exitno));
1775 k = emit_isk12((8*topslot));
1776 lua_assert(k);
1777 emit_n(as, A64I_CMPx^k, RID_TMP);
1778 emit_dnm(as, A64I_SUBx, RID_TMP, RID_TMP, pbase);
1779 emit_lso(as, A64I_LDRx, RID_TMP, RID_TMP,
1780 (int32_t)offsetof(lua_State, maxstack));
1781 if (irp) { /* Must not spill arbitrary registers in head of side trace. */
1782 if (ra_hasspill(irp->s))
1783 emit_lso(as, A64I_LDRx, pbase, RID_SP, sps_scale(irp->s));
1784 emit_lso(as, A64I_LDRx, RID_TMP, RID_GL, glofs(as, &J2G(as->J)->cur_L));
1785 if (ra_hasspill(irp->s) && !allow)
1786 emit_lso(as, A64I_STRx, RID_RET, RID_SP, 0); /* Save temp register. */
1787 } else {
1788 emit_getgl(as, RID_TMP, cur_L);
1789 }
1790}
1791
1792/* Restore Lua stack from on-trace state. */
1793static void asm_stack_restore(ASMState *as, SnapShot *snap)
1794{
1795 SnapEntry *map = &as->T->snapmap[snap->mapofs];
1796#ifdef LUA_USE_ASSERT
1797 SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1-LJ_FR2];
1798#endif
1799 MSize n, nent = snap->nent;
1800 /* Store the value of all modified slots to the Lua stack. */
1801 for (n = 0; n < nent; n++) {
1802 SnapEntry sn = map[n];
1803 BCReg s = snap_slot(sn);
1804 int32_t ofs = 8*((int32_t)s-1-LJ_FR2);
1805 IRRef ref = snap_ref(sn);
1806 IRIns *ir = IR(ref);
1807 if ((sn & SNAP_NORESTORE))
1808 continue;
1809 if (irt_isnum(ir->t)) {
1810 Reg src = ra_alloc1(as, ref, RSET_FPR);
1811 emit_lso(as, A64I_STRd, (src & 31), RID_BASE, ofs);
1812 } else {
1813 asm_tvstore64(as, RID_BASE, ofs, ref);
1814 }
1815 checkmclim(as);
1816 }
1817 lua_assert(map + nent == flinks);
1818}
1819
1820/* -- GC handling --------------------------------------------------------- */
1821
1822/* Check GC threshold and do one or more GC steps. */
1823static void asm_gc_check(ASMState *as)
1824{
1825 const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
1826 IRRef args[2];
1827 MCLabel l_end;
1828 Reg tmp1, tmp2;
1829 ra_evictset(as, RSET_SCRATCH);
1830 l_end = emit_label(as);
1831 /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
1832 asm_guardcnb(as, A64I_CBNZ, RID_RET); /* Assumes asm_snap_prep() is done. */
1833 args[0] = ASMREF_TMP1; /* global_State *g */
1834 args[1] = ASMREF_TMP2; /* MSize steps */
1835 asm_gencall(as, ci, args);
1836 tmp1 = ra_releasetmp(as, ASMREF_TMP1);
1837 tmp2 = ra_releasetmp(as, ASMREF_TMP2);
1838 emit_loadi(as, tmp2, as->gcsteps);
1839 /* Jump around GC step if GC total < GC threshold. */
1840 emit_cond_branch(as, CC_LS, l_end);
1841 emit_nm(as, A64I_CMPx, RID_TMP, tmp2);
1842 emit_lso(as, A64I_LDRx, tmp2, tmp1,
1843 (int32_t)offsetof(global_State, gc.threshold));
1844 emit_lso(as, A64I_LDRx, RID_TMP, tmp1,
1845 (int32_t)offsetof(global_State, gc.total));
1846 ra_allockreg(as, i64ptr(J2G(as->J)), tmp1);
1847 as->gcsteps = 0;
1848 checkmclim(as);
1849}
1850
1851/* -- Loop handling ------------------------------------------------------- */
1852
1853/* Fixup the loop branch. */
1854static void asm_loop_fixup(ASMState *as)
1855{
1856 MCode *p = as->mctop;
1857 MCode *target = as->mcp;
1858 if (as->loopinv) { /* Inverted loop branch? */
1859 uint32_t mask = (p[-2] & 0x7e000000) == 0x36000000 ? 0x3fffu : 0x7ffffu;
1860 ptrdiff_t delta = target - (p - 2);
1861 /* asm_guard* already inverted the bcc/tnb/cnb and patched the final b. */
1862 p[-2] |= ((uint32_t)delta & mask) << 5;
1863 } else {
1864 ptrdiff_t delta = target - (p - 1);
1865 p[-1] = A64I_B | A64F_S26(delta);
1866 }
1867}
1868
1869/* -- Head of trace ------------------------------------------------------- */
1870
1871/* Reload L register from g->cur_L. */
1872static void asm_head_lreg(ASMState *as)
1873{
1874 IRIns *ir = IR(ASMREF_L);
1875 if (ra_used(ir)) {
1876 Reg r = ra_dest(as, ir, RSET_GPR);
1877 emit_getgl(as, r, cur_L);
1878 ra_evictk(as);
1879 }
1880}
1881
1882/* Coalesce BASE register for a root trace. */
1883static void asm_head_root_base(ASMState *as)
1884{
1885 IRIns *ir;
1886 asm_head_lreg(as);
1887 ir = IR(REF_BASE);
1888 if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
1889 ra_spill(as, ir);
1890 ra_destreg(as, ir, RID_BASE);
1891}
1892
1893/* Coalesce BASE register for a side trace. */
1894static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
1895{
1896 IRIns *ir;
1897 asm_head_lreg(as);
1898 ir = IR(REF_BASE);
1899 if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
1900 ra_spill(as, ir);
1901 if (ra_hasspill(irp->s)) {
1902 rset_clear(allow, ra_dest(as, ir, allow));
1903 } else {
1904 Reg r = irp->r;
1905 lua_assert(ra_hasreg(r));
1906 rset_clear(allow, r);
1907 if (r != ir->r && !rset_test(as->freeset, r))
1908 ra_restore(as, regcost_ref(as->cost[r]));
1909 ra_destreg(as, ir, r);
1910 }
1911 return allow;
1912}
1913
1914/* -- Tail of trace ------------------------------------------------------- */
1915
1916/* Fixup the tail code. */
1917static void asm_tail_fixup(ASMState *as, TraceNo lnk)
1918{
1919 MCode *p = as->mctop;
1920 MCode *target;
1921 /* Undo the sp adjustment in BC_JLOOP when exiting to the interpreter. */
1922 int32_t spadj = as->T->spadjust + (lnk ? 0 : sps_scale(SPS_FIXED));
1923 if (spadj == 0) {
1924 *--p = A64I_LE(A64I_NOP);
1925 as->mctop = p;
1926 } else {
1927 /* Patch stack adjustment. */
1928 uint32_t k = emit_isk12(spadj);
1929 lua_assert(k);
1930 p[-2] = (A64I_ADDx^k) | A64F_D(RID_SP) | A64F_N(RID_SP);
1931 }
1932 /* Patch exit branch. */
1933 target = lnk ? traceref(as->J, lnk)->mcode : (MCode *)lj_vm_exit_interp;
1934 p[-1] = A64I_B | A64F_S26((target-p)+1);
1935}
1936
1937/* Prepare tail of code. */
1938static void asm_tail_prep(ASMState *as)
1939{
1940 MCode *p = as->mctop - 1; /* Leave room for exit branch. */
1941 if (as->loopref) {
1942 as->invmcp = as->mcp = p;
1943 } else {
1944 as->mcp = p-1; /* Leave room for stack pointer adjustment. */
1945 as->invmcp = NULL;
1946 }
1947 *p = 0; /* Prevent load/store merging. */
1948}
1949
1950/* -- Trace setup --------------------------------------------------------- */
1951
1952/* Ensure there are enough stack slots for call arguments. */
1953static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
1954{
1955 IRRef args[CCI_NARGS_MAX*2];
1956 uint32_t i, nargs = CCI_XNARGS(ci);
1957 int nslots = 0, ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
1958 asm_collectargs(as, ir, ci, args);
1959 for (i = 0; i < nargs; i++) {
1960 if (args[i] && irt_isfp(IR(args[i])->t)) {
1961 if (nfpr > 0) nfpr--; else nslots += 2;
1962 } else {
1963 if (ngpr > 0) ngpr--; else nslots += 2;
1964 }
1965 }
1966 if (nslots > as->evenspill) /* Leave room for args in stack slots. */
1967 as->evenspill = nslots;
1968 return REGSP_HINT(RID_RET);
1969}
1970
1971static void asm_setup_target(ASMState *as)
1972{
1973 /* May need extra exit for asm_stack_check on side traces. */
1974 asm_exitstub_setup(as, as->T->nsnap + (as->parent ? 1 : 0));
1975}
1976
1977#if LJ_BE
1978/* ARM64 instructions are always little-endian. Swap for ARM64BE. */
1979static void asm_mcode_fixup(MCode *mcode, MSize size)
1980{
1981 MCode *pe = (MCode *)((char *)mcode + size);
1982 while (mcode < pe) {
1983 MCode ins = *mcode;
1984 *mcode++ = lj_bswap(ins);
1985 }
1986}
1987#define LJ_TARGET_MCODE_FIXUP 1
1988#endif
1989
1990/* -- Trace patching ------------------------------------------------------ */
1991
1992/* Patch exit jumps of existing machine code to a new target. */
1993void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
1994{
1995 MCode *p = T->mcode;
1996 MCode *pe = (MCode *)((char *)p + T->szmcode);
1997 MCode *cstart = NULL;
1998 MCode *mcarea = lj_mcode_patch(J, p, 0);
1999 MCode *px = exitstub_trace_addr(T, exitno);
2000 /* Note: this assumes a trace exit is only ever patched once. */
2001 for (; p < pe; p++) {
2002 /* Look for exitstub branch, replace with branch to target. */
2003 ptrdiff_t delta = target - p;
2004 MCode ins = A64I_LE(*p);
2005 if ((ins & 0xff000000u) == 0x54000000u &&
2006 ((ins ^ ((px-p)<<5)) & 0x00ffffe0u) == 0) {
2007 /* Patch bcc, if within range. */
2008 if (A64F_S_OK(delta, 19)) {
2009 *p = A64I_LE((ins & 0xff00001fu) | A64F_S19(delta));
2010 if (!cstart) cstart = p;
2011 }
2012 } else if ((ins & 0xfc000000u) == 0x14000000u &&
2013 ((ins ^ (px-p)) & 0x03ffffffu) == 0) {
2014 /* Patch b. */
2015 lua_assert(A64F_S_OK(delta, 26));
2016 *p = A64I_LE((ins & 0xfc000000u) | A64F_S26(delta));
2017 if (!cstart) cstart = p;
2018 } else if ((ins & 0x7e000000u) == 0x34000000u &&
2019 ((ins ^ ((px-p)<<5)) & 0x00ffffe0u) == 0) {
2020 /* Patch cbz/cbnz, if within range. */
2021 if (A64F_S_OK(delta, 19)) {
2022 *p = A64I_LE((ins & 0xff00001fu) | A64F_S19(delta));
2023 if (!cstart) cstart = p;
2024 }
2025 } else if ((ins & 0x7e000000u) == 0x36000000u &&
2026 ((ins ^ ((px-p)<<5)) & 0x0007ffe0u) == 0) {
2027 /* Patch tbz/tbnz, if within range. */
2028 if (A64F_S_OK(delta, 14)) {
2029 *p = A64I_LE((ins & 0xfff8001fu) | A64F_S14(delta));
2030 if (!cstart) cstart = p;
2031 }
2032 }
2033 }
2034 { /* Always patch long-range branch in exit stub itself. */
2035 ptrdiff_t delta = target - px;
2036 lua_assert(A64F_S_OK(delta, 26));
2037 *px = A64I_B | A64F_S26(delta);
2038 if (!cstart) cstart = px;
2039 }
2040 lj_mcode_sync(cstart, px+1);
2041 lj_mcode_patch(J, mcarea, 1);
2042}
2043
generated by cgit v1.2.3-55-g6feb (git 2.39.1) at 2025-04-25 15:34:17 +0000