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authorcvs2svn <admin@example.com>2025-04-14 17:32:06 +0000
committercvs2svn <admin@example.com>2025-04-14 17:32:06 +0000
commiteb8dd9dca1228af0cd132f515509051ecfabf6f6 (patch)
treeedb6da6af7e865d488dc1a29309f1e1ec226e603 /src/lib/libcrypto/arch/amd64
parent247f0352e0ed72a4f476db9dc91f4d982bc83eb2 (diff)
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This commit was manufactured by cvs2git to create tag 'tb_20250414'.tb_20250414
Diffstat (limited to 'src/lib/libcrypto/arch/amd64')
-rw-r--r--src/lib/libcrypto/arch/amd64/Makefile.inc68
-rw-r--r--src/lib/libcrypto/arch/amd64/crypto_arch.h54
-rw-r--r--src/lib/libcrypto/arch/amd64/crypto_cpu_caps.c134
-rw-r--r--src/lib/libcrypto/arch/amd64/opensslconf.h149
4 files changed, 0 insertions, 405 deletions
diff --git a/src/lib/libcrypto/arch/amd64/Makefile.inc b/src/lib/libcrypto/arch/amd64/Makefile.inc
deleted file mode 100644
index b1a6563931..0000000000
--- a/src/lib/libcrypto/arch/amd64/Makefile.inc
+++ /dev/null
@@ -1,68 +0,0 @@
1# $OpenBSD: Makefile.inc,v 1.37 2025/02/14 12:01:58 jsing Exp $
2
3# amd64-specific libcrypto build rules
4
5# all amd64 code generators use this
6EXTRA_PL = ${LCRYPTO_SRC}/perlasm/x86_64-xlate.pl
7
8SRCS += crypto_cpu_caps.c
9
10# aes
11CFLAGS+= -DAES_ASM
12SSLASM+= aes aes-x86_64
13CFLAGS+= -DBSAES_ASM
14SSLASM+= aes bsaes-x86_64
15CFLAGS+= -DVPAES_ASM
16SSLASM+= aes vpaes-x86_64
17SSLASM+= aes aesni-x86_64
18# bn
19CFLAGS+= -DOPENSSL_IA32_SSE2
20CFLAGS+= -DRSA_ASM
21SSLASM+= bn modexp512-x86_64
22CFLAGS+= -DOPENSSL_BN_ASM_MONT
23SSLASM+= bn x86_64-mont
24CFLAGS+= -DOPENSSL_BN_ASM_MONT5
25SSLASM+= bn x86_64-mont5
26
27# bn s2n-bignum
28SRCS += bn_arch.c
29SRCS += bignum_add.S
30SRCS += bignum_cmadd.S
31SRCS += bignum_cmul.S
32SRCS += bignum_mul.S
33SRCS += bignum_mul_4_8_alt.S
34SRCS += bignum_mul_8_16_alt.S
35SRCS += bignum_sqr.S
36SRCS += bignum_sqr_4_8_alt.S
37SRCS += bignum_sqr_8_16_alt.S
38SRCS += bignum_sub.S
39SRCS += word_clz.S
40
41# md5
42CFLAGS+= -DMD5_ASM
43SRCS+= md5_amd64_generic.S
44# modes
45CFLAGS+= -DGHASH_ASM
46SSLASM+= modes ghash-x86_64
47# rc4
48SSLASM+= rc4 rc4-x86_64
49# ripemd
50# sha
51SRCS+= sha1_amd64.c
52SRCS+= sha1_amd64_generic.S
53SRCS+= sha1_amd64_shani.S
54SRCS+= sha256_amd64.c
55SRCS+= sha256_amd64_generic.S
56SRCS+= sha256_amd64_shani.S
57SRCS+= sha512_amd64.c
58SRCS+= sha512_amd64_generic.S
59
60.for dir f in ${SSLASM}
61SRCS+= ${f}.S
62GENERATED+=${f}.S
63${f}.S: ${LCRYPTO_SRC}/${dir}/asm/${f}.pl ${EXTRA_PL}
64 (cd ${LCRYPTO_SRC}/${dir} ; \
65 /usr/bin/perl ./asm/${f}.pl openbsd) > ${.TARGET}
66.endfor
67
68CFLAGS+=-fret-clean
diff --git a/src/lib/libcrypto/arch/amd64/crypto_arch.h b/src/lib/libcrypto/arch/amd64/crypto_arch.h
deleted file mode 100644
index 951374250d..0000000000
--- a/src/lib/libcrypto/arch/amd64/crypto_arch.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/* $OpenBSD: crypto_arch.h,v 1.5 2025/02/14 12:01:58 jsing Exp $ */
2/*
3 * Copyright (c) 2024 Joel Sing <jsing@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <stdint.h>
19
20#ifndef HEADER_CRYPTO_ARCH_H
21#define HEADER_CRYPTO_ARCH_H
22
23#define HAVE_CRYPTO_CPU_CAPS_INIT
24#define HAVE_CRYPTO_CPU_CAPS_IA32
25
26#ifndef __ASSEMBLER__
27extern uint64_t crypto_cpu_caps_amd64;
28#endif
29
30#define CRYPTO_CPU_CAPS_AMD64_SHA (1ULL << 0)
31
32#ifndef OPENSSL_NO_ASM
33
34#define HAVE_AES_CBC_ENCRYPT_INTERNAL
35#define HAVE_AES_SET_ENCRYPT_KEY_INTERNAL
36#define HAVE_AES_SET_DECRYPT_KEY_INTERNAL
37#define HAVE_AES_ENCRYPT_INTERNAL
38#define HAVE_AES_DECRYPT_INTERNAL
39
40#define HAVE_RC4_INTERNAL
41#define HAVE_RC4_SET_KEY_INTERNAL
42
43#define HAVE_SHA1_BLOCK_DATA_ORDER
44#define HAVE_SHA1_BLOCK_GENERIC
45
46#define HAVE_SHA256_BLOCK_DATA_ORDER
47#define HAVE_SHA256_BLOCK_GENERIC
48
49#define HAVE_SHA512_BLOCK_DATA_ORDER
50#define HAVE_SHA512_BLOCK_GENERIC
51
52#endif
53
54#endif
diff --git a/src/lib/libcrypto/arch/amd64/crypto_cpu_caps.c b/src/lib/libcrypto/arch/amd64/crypto_cpu_caps.c
deleted file mode 100644
index 63b7b64cda..0000000000
--- a/src/lib/libcrypto/arch/amd64/crypto_cpu_caps.c
+++ /dev/null
@@ -1,134 +0,0 @@
1/* $OpenBSD: crypto_cpu_caps.c,v 1.4 2024/11/16 13:05:35 jsing Exp $ */
2/*
3 * Copyright (c) 2024 Joel Sing <jsing@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <stdio.h>
19
20#include <openssl/crypto.h>
21
22#include "crypto_arch.h"
23#include "x86_arch.h"
24
25/* Legacy architecture specific capabilities, used by perlasm. */
26uint64_t OPENSSL_ia32cap_P;
27
28/* Machine dependent CPU capabilities. */
29uint64_t crypto_cpu_caps_amd64;
30
31/* Machine independent CPU capabilities. */
32extern uint64_t crypto_cpu_caps;
33
34static inline void
35cpuid(uint32_t eax, uint32_t *out_eax, uint32_t *out_ebx, uint32_t *out_ecx,
36 uint32_t *out_edx)
37{
38 uint32_t ebx = 0, ecx = 0, edx = 0;
39
40#ifndef OPENSSL_NO_ASM
41 __asm__ ("cpuid": "+a"(eax), "+b"(ebx), "+c"(ecx), "+d"(edx));
42#else
43 eax = 0;
44#endif
45
46 if (out_eax != NULL)
47 *out_eax = eax;
48 if (out_ebx != NULL)
49 *out_ebx = ebx;
50 if (out_ecx != NULL)
51 *out_ecx = ecx;
52 if (out_edx != NULL)
53 *out_edx = edx;
54}
55
56static inline void
57xgetbv(uint32_t ecx, uint32_t *out_eax, uint32_t *out_edx)
58{
59 uint32_t eax = 0, edx = 0;
60
61#ifndef OPENSSL_NO_ASM
62 __asm__ ("xgetbv": "+a"(eax), "+c"(ecx), "+d"(edx));
63#endif
64
65 if (out_eax != NULL)
66 *out_eax = eax;
67 if (out_edx != NULL)
68 *out_edx = edx;
69}
70
71void
72crypto_cpu_caps_init(void)
73{
74 uint32_t eax, ebx, ecx, edx, max_cpuid;
75 uint64_t caps = 0;
76
77 cpuid(0, &eax, &ebx, &ecx, &edx);
78
79 max_cpuid = eax;
80
81 /* "GenuineIntel" in little endian. */
82 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
83 caps |= CPUCAP_MASK_INTEL;
84
85 if (max_cpuid < 1)
86 return;
87
88 cpuid(1, &eax, NULL, &ecx, &edx);
89
90 if ((edx & IA32CAP_MASK0_FXSR) != 0)
91 caps |= CPUCAP_MASK_FXSR;
92 if ((edx & IA32CAP_MASK0_HT) != 0)
93 caps |= CPUCAP_MASK_HT;
94 if ((edx & IA32CAP_MASK0_MMX) != 0)
95 caps |= CPUCAP_MASK_MMX;
96 if ((edx & IA32CAP_MASK0_SSE) != 0)
97 caps |= CPUCAP_MASK_SSE;
98 if ((edx & IA32CAP_MASK0_SSE2) != 0)
99 caps |= CPUCAP_MASK_SSE2;
100
101 if ((ecx & IA32CAP_MASK1_AESNI) != 0)
102 caps |= CPUCAP_MASK_AESNI;
103 if ((ecx & IA32CAP_MASK1_PCLMUL) != 0)
104 caps |= CPUCAP_MASK_PCLMUL;
105 if ((ecx & IA32CAP_MASK1_SSSE3) != 0)
106 caps |= CPUCAP_MASK_SSSE3;
107
108 /* AVX requires OSXSAVE and XMM/YMM state to be enabled. */
109 if ((ecx & IA32CAP_MASK1_OSXSAVE) != 0) {
110 xgetbv(0, &eax, NULL);
111 if (((eax >> 1) & 3) == 3 && (ecx & IA32CAP_MASK1_AVX) != 0)
112 caps |= CPUCAP_MASK_AVX;
113 }
114
115 if (max_cpuid >= 7) {
116 cpuid(7, NULL, &ebx, NULL, NULL);
117
118 /* Intel SHA extensions feature bit - ebx[29]. */
119 if (((ebx >> 29) & 1) != 0)
120 crypto_cpu_caps_amd64 |= CRYPTO_CPU_CAPS_AMD64_SHA;
121 }
122
123 /* Set machine independent CPU capabilities. */
124 if ((caps & CPUCAP_MASK_AESNI) != 0)
125 crypto_cpu_caps |= CRYPTO_CPU_CAPS_ACCELERATED_AES;
126
127 OPENSSL_ia32cap_P = caps;
128}
129
130uint64_t
131crypto_cpu_caps_ia32(void)
132{
133 return OPENSSL_ia32cap_P;
134}
diff --git a/src/lib/libcrypto/arch/amd64/opensslconf.h b/src/lib/libcrypto/arch/amd64/opensslconf.h
deleted file mode 100644
index cc193762f1..0000000000
--- a/src/lib/libcrypto/arch/amd64/opensslconf.h
+++ /dev/null
@@ -1,149 +0,0 @@
1#include <openssl/opensslfeatures.h>
2/* crypto/opensslconf.h.in */
3
4#if defined(HEADER_CRYPTO_LOCAL_H) && !defined(OPENSSLDIR)
5#define OPENSSLDIR "/etc/ssl"
6#endif
7
8#undef OPENSSL_EXPORT_VAR_AS_FUNCTION
9
10#ifndef OPENSSL_FILE
11#ifdef OPENSSL_NO_FILENAMES
12#define OPENSSL_FILE ""
13#define OPENSSL_LINE 0
14#else
15#define OPENSSL_FILE __FILE__
16#define OPENSSL_LINE __LINE__
17#endif
18#endif
19
20#if defined(HEADER_IDEA_H) && !defined(IDEA_INT)
21#define IDEA_INT unsigned int
22#endif
23
24#if defined(HEADER_MD2_H) && !defined(MD2_INT)
25#define MD2_INT unsigned int
26#endif
27
28#if defined(HEADER_RC2_H) && !defined(RC2_INT)
29/* I need to put in a mod for the alpha - eay */
30#define RC2_INT unsigned int
31#endif
32
33#if defined(HEADER_RC4_H)
34#if !defined(RC4_INT)
35/* using int types make the structure larger but make the code faster
36 * on most boxes I have tested - up to %20 faster. */
37/*
38 * I don't know what does "most" mean, but declaring "int" is a must on:
39 * - Intel P6 because partial register stalls are very expensive;
40 * - elder Alpha because it lacks byte load/store instructions;
41 */
42#define RC4_INT unsigned int
43#endif
44#if !defined(RC4_CHUNK)
45/*
46 * This enables code handling data aligned at natural CPU word
47 * boundary. See crypto/rc4/rc4_enc.c for further details.
48 */
49#define RC4_CHUNK unsigned long
50#endif
51#endif
52
53#if (defined(HEADER_NEW_DES_H) || defined(HEADER_DES_H)) && !defined(DES_LONG)
54/* If this is set to 'unsigned int' on a DEC Alpha, this gives about a
55 * %20 speed up (longs are 8 bytes, int's are 4). */
56#ifndef DES_LONG
57#define DES_LONG unsigned int
58#endif
59#endif
60
61#if defined(HEADER_BN_H) && !defined(CONFIG_HEADER_BN_H)
62#define CONFIG_HEADER_BN_H
63#undef BN_LLONG
64
65/* Should we define BN_DIV2W here? */
66
67/* Only one for the following should be defined */
68#define SIXTY_FOUR_BIT_LONG
69#undef SIXTY_FOUR_BIT
70#undef THIRTY_TWO_BIT
71#endif
72
73#if defined(HEADER_BF_LOCL_H) && !defined(CONFIG_HEADER_BF_LOCL_H)
74#define CONFIG_HEADER_BF_LOCL_H
75#undef BF_PTR
76#endif /* HEADER_BF_LOCL_H */
77
78#if defined(HEADER_DES_LOCL_H) && !defined(CONFIG_HEADER_DES_LOCL_H)
79#define CONFIG_HEADER_DES_LOCL_H
80#ifndef DES_DEFAULT_OPTIONS
81/* the following is tweaked from a config script, that is why it is a
82 * protected undef/define */
83#ifndef DES_PTR
84#undef DES_PTR
85#endif
86
87/* This helps C compiler generate the correct code for multiple functional
88 * units. It reduces register dependencies at the expense of 2 more
89 * registers */
90#ifndef DES_RISC1
91#undef DES_RISC1
92#endif
93
94#ifndef DES_RISC2
95#undef DES_RISC2
96#endif
97
98#if defined(DES_RISC1) && defined(DES_RISC2)
99YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!!
100#endif
101
102/* Unroll the inner loop, this sometimes helps, sometimes hinders.
103 * Very much CPU dependent */
104#ifndef DES_UNROLL
105#define DES_UNROLL
106#endif
107
108/* These default values were supplied by
109 * Peter Gutman <pgut001@cs.auckland.ac.nz>
110 * They are only used if nothing else has been defined */
111#if !defined(DES_PTR) && !defined(DES_RISC1) && !defined(DES_RISC2) && !defined(DES_UNROLL)
112/* Special defines which change the way the code is built depending on the
113 CPU and OS. For SGI machines you can use _MIPS_SZLONG (32 or 64) to find
114 even newer MIPS CPU's, but at the moment one size fits all for
115 optimization options. Older Sparc's work better with only UNROLL, but
116 there's no way to tell at compile time what it is you're running on */
117
118#if defined( sun ) /* Newer Sparc's */
119# define DES_PTR
120# define DES_RISC1
121# define DES_UNROLL
122#elif defined( __ultrix ) /* Older MIPS */
123# define DES_PTR
124# define DES_RISC2
125# define DES_UNROLL
126#elif defined( __osf1__ ) /* Alpha */
127# define DES_PTR
128# define DES_RISC2
129#elif defined ( _AIX ) /* RS6000 */
130 /* Unknown */
131#elif defined( __hpux ) /* HP-PA */
132 /* Unknown */
133#elif defined( __aux ) /* 68K */
134 /* Unknown */
135#elif defined( __dgux ) /* 88K (but P6 in latest boxes) */
136# define DES_UNROLL
137#elif defined( __sgi ) /* Newer MIPS */
138# define DES_PTR
139# define DES_RISC2
140# define DES_UNROLL
141#elif defined(i386) || defined(__i386__) /* x86 boxes, should be gcc */
142# define DES_PTR
143# define DES_RISC1
144# define DES_UNROLL
145#endif /* Systems-specific speed defines */
146#endif
147
148#endif /* DES_DEFAULT_OPTIONS */
149#endif /* HEADER_DES_LOCL_H */