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authorpatrick <>2019-07-02 19:31:28 +0000
committerpatrick <>2019-07-02 19:31:28 +0000
commit88ab3711341dea97a3118b0654ceab1679d5e0a1 (patch)
tree402e4d2faadaa1bec334a1353f0221180cea6aaf /src/lib/libcrypto/arm64cpuid.S
parent2bfac65cc0bd40d261de39c1b0f01b8955de1d1f (diff)
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Add cpuid support for arm64 so that we can recognize which
hardware crypto features are available. "no objections" kettenis@
Diffstat (limited to 'src/lib/libcrypto/arm64cpuid.S')
-rw-r--r--src/lib/libcrypto/arm64cpuid.S47
1 files changed, 47 insertions, 0 deletions
diff --git a/src/lib/libcrypto/arm64cpuid.S b/src/lib/libcrypto/arm64cpuid.S
new file mode 100644
index 0000000000..5eeff91c6e
--- /dev/null
+++ b/src/lib/libcrypto/arm64cpuid.S
@@ -0,0 +1,47 @@
1#include "arm_arch.h"
2
3.text
4.arch armv8-a+crypto+sha3
5
6.align 5
7.globl _armv7_neon_probe
8.type _armv7_neon_probe,%function
9_armv7_neon_probe:
10 orr v15.16b, v15.16b, v15.16b
11 ret
12.size _armv7_neon_probe,.-_armv7_neon_probe
13
14.globl _armv8_aes_probe
15.type _armv8_aes_probe,%function
16_armv8_aes_probe:
17 aese v0.16b, v0.16b
18 ret
19.size _armv8_aes_probe,.-_armv8_aes_probe
20
21.globl _armv8_sha1_probe
22.type _armv8_sha1_probe,%function
23_armv8_sha1_probe:
24 sha1h s0, s0
25 ret
26.size _armv8_sha1_probe,.-_armv8_sha1_probe
27
28.globl _armv8_sha256_probe
29.type _armv8_sha256_probe,%function
30_armv8_sha256_probe:
31 sha256su0 v0.4s, v0.4s
32 ret
33.size _armv8_sha256_probe,.-_armv8_sha256_probe
34
35.globl _armv8_pmull_probe
36.type _armv8_pmull_probe,%function
37_armv8_pmull_probe:
38 pmull v0.1q, v0.1d, v0.1d
39 ret
40.size _armv8_pmull_probe,.-_armv8_pmull_probe
41
42.globl _armv8_sha512_probe
43.type _armv8_sha512_probe,%function
44_armv8_sha512_probe:
45 sha512su0 v0.2d,v0.2d
46 ret
47.size _armv8_sha512_probe,.-_armv8_sha512_probe