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authormiod <>2016-11-04 17:30:30 +0000
committermiod <>2016-11-04 17:30:30 +0000
commit723502d9588ba0e1cc08af1b12654917da74d440 (patch)
tree77b413175d422148cfb0ef7b2062340230aa5413 /src/lib/libcrypto/rc4/asm
parent391f8ce21bb7929810460a73e2fde2c80540848d (diff)
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Replace all uses of magic numbers when operating on OPENSSL_ia32_P[] by
meaningful constants in a private header file, so that reviewers can actually get a chance to figure out what the code is attempting to do without knowing all cpuid bits. While there, turn it from an array of two 32-bit ints into a properly aligned 64-bit int. Use of OPENSSL_ia32_P is now restricted to the assembler parts. C code will now always use OPENSSL_cpu_caps() and check for the proper bits in the whole 64-bit word it returns. i386 tests and ok jsing@
Diffstat (limited to 'src/lib/libcrypto/rc4/asm')
-rw-r--r--src/lib/libcrypto/rc4/asm/rc4-586.pl9
-rwxr-xr-xsrc/lib/libcrypto/rc4/asm/rc4-x86_64.pl9
2 files changed, 10 insertions, 8 deletions
diff --git a/src/lib/libcrypto/rc4/asm/rc4-586.pl b/src/lib/libcrypto/rc4/asm/rc4-586.pl
index 84f1a798cb..03f0cff467 100644
--- a/src/lib/libcrypto/rc4/asm/rc4-586.pl
+++ b/src/lib/libcrypto/rc4/asm/rc4-586.pl
@@ -189,7 +189,8 @@ if ($alt=0) {
189 &jz (&label("go4loop4")); 189 &jz (&label("go4loop4"));
190 190
191 &picmeup($out,"OPENSSL_ia32cap_P"); 191 &picmeup($out,"OPENSSL_ia32cap_P");
192 &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX] 192 # check SSE2 bit [could have been MMX]
193 &bt (&DWP(0,$out),"\$IA32CAP_BIT0_SSE2");
193 &jnc (&label("go4loop4")); 194 &jnc (&label("go4loop4"));
194 195
195 &mov ($out,&wparam(3)) if (!$alt); 196 &mov ($out,&wparam(3)) if (!$alt);
@@ -312,7 +313,7 @@ $idx="edx";
312 &xor ("eax","eax"); 313 &xor ("eax","eax");
313 &mov (&DWP(-4,$out),$idi); # borrow key->y 314 &mov (&DWP(-4,$out),$idi); # borrow key->y
314 315
315 &bt (&DWP(0,$idx),20); # check for bit#20 316 &bt (&DWP(0,$idx),"\$IA32CAP_BIT0_INTELP4");
316 &jc (&label("c1stloop")); 317 &jc (&label("c1stloop"));
317 318
318&set_label("w1stloop",16); 319&set_label("w1stloop",16);
@@ -388,9 +389,9 @@ $idx="edx";
388 &lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax")); 389 &lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax"));
389 &picmeup("edx","OPENSSL_ia32cap_P"); 390 &picmeup("edx","OPENSSL_ia32cap_P");
390 &mov ("edx",&DWP(0,"edx")); 391 &mov ("edx",&DWP(0,"edx"));
391 &bt ("edx",20); 392 &bt ("edx","\$IA32CAP_BIT0_INTELP4");
392 &jc (&label("1xchar")); 393 &jc (&label("1xchar"));
393 &bt ("edx",26); 394 &bt ("edx","\$IA32CAP_BIT0_SSE2");
394 &jnc (&label("ret")); 395 &jnc (&label("ret"));
395 &add ("eax",25); 396 &add ("eax",25);
396 &ret (); 397 &ret ();
diff --git a/src/lib/libcrypto/rc4/asm/rc4-x86_64.pl b/src/lib/libcrypto/rc4/asm/rc4-x86_64.pl
index 197749dda7..2135b38ef8 100755
--- a/src/lib/libcrypto/rc4/asm/rc4-x86_64.pl
+++ b/src/lib/libcrypto/rc4/asm/rc4-x86_64.pl
@@ -122,6 +122,7 @@ $out="%rcx"; # arg4
122$code=<<___; 122$code=<<___;
123.text 123.text
124.extern OPENSSL_ia32cap_P 124.extern OPENSSL_ia32cap_P
125.hidden OPENSSL_ia32cap_P
125 126
126.globl RC4 127.globl RC4
127.type RC4,\@function,4 128.type RC4,\@function,4
@@ -164,7 +165,7 @@ $code.=<<___;
164 movl ($dat,$XX[0],4),$TX[0]#d 165 movl ($dat,$XX[0],4),$TX[0]#d
165 test \$-16,$len 166 test \$-16,$len
166 jz .Lloop1 167 jz .Lloop1
167 bt \$30,%r8d # Intel CPU? 168 bt \$IA32CAP_BIT0_INTEL,%r8d # Intel CPU?
168 jc .Lintel 169 jc .Lintel
169 and \$7,$TX[1] 170 and \$7,$TX[1]
170 lea 1($XX[0]),$XX[1] 171 lea 1($XX[0]),$XX[1]
@@ -442,7 +443,7 @@ RC4_set_key:
442 xor %r11,%r11 443 xor %r11,%r11
443 444
444 mov OPENSSL_ia32cap_P(%rip),$idx#d 445 mov OPENSSL_ia32cap_P(%rip),$idx#d
445 bt \$20,$idx#d # RC4_CHAR? 446 bt \$IA32CAP_BIT0_INTELP4,$idx#d # RC4_CHAR?
446 jc .Lc1stloop 447 jc .Lc1stloop
447 jmp .Lw1stloop 448 jmp .Lw1stloop
448 449
@@ -506,9 +507,9 @@ RC4_set_key:
506RC4_options: 507RC4_options:
507 lea .Lopts(%rip),%rax 508 lea .Lopts(%rip),%rax
508 mov OPENSSL_ia32cap_P(%rip),%edx 509 mov OPENSSL_ia32cap_P(%rip),%edx
509 bt \$20,%edx 510 bt \$IA32CAP_BIT0_INTELP4,%edx
510 jc .L8xchar 511 jc .L8xchar
511 bt \$30,%edx 512 bt \$IA32CAP_BIT0_INTEL,%edx
512 jnc .Ldone 513 jnc .Ldone
513 add \$25,%rax 514 add \$25,%rax
514 ret 515 ret