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author | jsing <> | 2024-10-18 13:36:24 +0000 |
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committer | jsing <> | 2024-10-18 13:36:24 +0000 |
commit | c3adbc1c81adde9927d8537128bb9cf20db03c1c (patch) | |
tree | 9f24e49a607732139a986f4abb3735d101835046 /src/lib/libcrypto/x86_arch.h | |
parent | 1a7fd7787292c0192e0f8e7889d78be38bf8c9c2 (diff) | |
download | openbsd-c3adbc1c81adde9927d8537128bb9cf20db03c1c.tar.gz openbsd-c3adbc1c81adde9927d8537128bb9cf20db03c1c.tar.bz2 openbsd-c3adbc1c81adde9927d8537128bb9cf20db03c1c.zip |
Provide crypto_cpu_caps_init() for amd64.
This is a CPU capability detection implementation in C, with minimal
inline assembly (for cpuid and xgetbv). This replaces the assembly
mess generated by x86_64cpuid.pl. Rather than populating OPENSSL_ia32cap_P
directly with CPUID output, just set the bits that the remaining
perlasm checks (namely AESNI, AVX, FXSR, INTEL, HT, MMX, PCLMUL, SSE, SSE2
and SSSE3).
ok joshua@ tb@
Diffstat (limited to 'src/lib/libcrypto/x86_arch.h')
-rw-r--r-- | src/lib/libcrypto/x86_arch.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/lib/libcrypto/x86_arch.h b/src/lib/libcrypto/x86_arch.h index 5b2cf97546..e9e9d48960 100644 --- a/src/lib/libcrypto/x86_arch.h +++ b/src/lib/libcrypto/x86_arch.h | |||
@@ -1,4 +1,4 @@ | |||
1 | /* $OpenBSD: x86_arch.h,v 1.1 2016/11/04 17:30:30 miod Exp $ */ | 1 | /* $OpenBSD: x86_arch.h,v 1.2 2024/10/18 13:36:24 jsing Exp $ */ |
2 | /* | 2 | /* |
3 | * Copyright (c) 2016 Miodrag Vallat. | 3 | * Copyright (c) 2016 Miodrag Vallat. |
4 | * | 4 | * |
@@ -76,15 +76,20 @@ | |||
76 | #define IA32CAP_MASK1_SSSE3 (1 << IA32CAP_BIT1_SSSE3) | 76 | #define IA32CAP_MASK1_SSSE3 (1 << IA32CAP_BIT1_SSSE3) |
77 | #define IA32CAP_MASK1_FMA3 (1 << IA32CAP_BIT1_FMA3) | 77 | #define IA32CAP_MASK1_FMA3 (1 << IA32CAP_BIT1_FMA3) |
78 | #define IA32CAP_MASK1_AESNI (1 << IA32CAP_BIT1_AESNI) | 78 | #define IA32CAP_MASK1_AESNI (1 << IA32CAP_BIT1_AESNI) |
79 | #define IA32CAP_MASK1_OSXSAVE (1 << IA32CAP_BIT1_OSXSAVE) | ||
79 | #define IA32CAP_MASK1_AVX (1 << IA32CAP_BIT1_AVX) | 80 | #define IA32CAP_MASK1_AVX (1 << IA32CAP_BIT1_AVX) |
80 | 81 | ||
81 | #define IA32CAP_MASK1_AMD_XOP (1 << IA32CAP_BIT1_AMD_XOP) | 82 | #define IA32CAP_MASK1_AMD_XOP (1 << IA32CAP_BIT1_AMD_XOP) |
82 | 83 | ||
83 | /* bit masks for OPENSSL_cpu_caps() */ | 84 | /* bit masks for OPENSSL_cpu_caps() */ |
85 | #define CPUCAP_MASK_HT IA32CAP_MASK0_HT | ||
84 | #define CPUCAP_MASK_MMX IA32CAP_MASK0_MMX | 86 | #define CPUCAP_MASK_MMX IA32CAP_MASK0_MMX |
85 | #define CPUCAP_MASK_FXSR IA32CAP_MASK0_FXSR | 87 | #define CPUCAP_MASK_FXSR IA32CAP_MASK0_FXSR |
86 | #define CPUCAP_MASK_SSE IA32CAP_MASK0_SSE | 88 | #define CPUCAP_MASK_SSE IA32CAP_MASK0_SSE |
89 | #define CPUCAP_MASK_SSE2 IA32CAP_MASK0_SSE2 | ||
90 | #define CPUCAP_MASK_INTEL IA32CAP_MASK0_INTEL | ||
87 | #define CPUCAP_MASK_INTELP4 IA32CAP_MASK0_INTELP4 | 91 | #define CPUCAP_MASK_INTELP4 IA32CAP_MASK0_INTELP4 |
88 | #define CPUCAP_MASK_PCLMUL (1ULL << (32 + IA32CAP_BIT1_PCLMUL)) | 92 | #define CPUCAP_MASK_PCLMUL (1ULL << (32 + IA32CAP_BIT1_PCLMUL)) |
89 | #define CPUCAP_MASK_SSSE3 (1ULL << (32 + IA32CAP_BIT1_SSSE3)) | 93 | #define CPUCAP_MASK_SSSE3 (1ULL << (32 + IA32CAP_BIT1_SSSE3)) |
90 | #define CPUCAP_MASK_AESNI (1ULL << (32 + IA32CAP_BIT1_AESNI)) | 94 | #define CPUCAP_MASK_AESNI (1ULL << (32 + IA32CAP_BIT1_AESNI)) |
95 | #define CPUCAP_MASK_AVX (1ULL << (32 + IA32CAP_BIT1_AVX)) | ||