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authormiod <>2015-11-14 14:53:14 +0000
committermiod <>2015-11-14 14:53:14 +0000
commite0c418d31d1c44cda609bf57ca974c612d5581a0 (patch)
tree92e79af9caccfc48d99025d2b33cb2938be77f99 /src/lib
parent89f84b7a8f6b99b4d8d6d4100b3313d12b601d31 (diff)
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mutli -> multi
Diffstat (limited to 'src/lib')
-rwxr-xr-xsrc/lib/libcrypto/sha/asm/sha512-ppc.pl2
-rwxr-xr-xsrc/lib/libssl/src/crypto/sha/asm/sha512-ppc.pl2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/lib/libcrypto/sha/asm/sha512-ppc.pl b/src/lib/libcrypto/sha/asm/sha512-ppc.pl
index f561f313c6..2a7d5a0e8b 100755
--- a/src/lib/libcrypto/sha/asm/sha512-ppc.pl
+++ b/src/lib/libcrypto/sha/asm/sha512-ppc.pl
@@ -20,7 +20,7 @@
20# 20#
21# (*) 64-bit code in 32-bit application context, which actually is 21# (*) 64-bit code in 32-bit application context, which actually is
22# on TODO list. It should be noted that for safe deployment in 22# on TODO list. It should be noted that for safe deployment in
23# 32-bit *mutli-threaded* context asynchronous signals should be 23# 32-bit *multi-threaded* context asynchronous signals should be
24# blocked upon entry to SHA512 block routine. This is because 24# blocked upon entry to SHA512 block routine. This is because
25# 32-bit signaling procedure invalidates upper halves of GPRs. 25# 32-bit signaling procedure invalidates upper halves of GPRs.
26# Context switch procedure preserves them, but not signaling:-( 26# Context switch procedure preserves them, but not signaling:-(
diff --git a/src/lib/libssl/src/crypto/sha/asm/sha512-ppc.pl b/src/lib/libssl/src/crypto/sha/asm/sha512-ppc.pl
index f561f313c6..2a7d5a0e8b 100755
--- a/src/lib/libssl/src/crypto/sha/asm/sha512-ppc.pl
+++ b/src/lib/libssl/src/crypto/sha/asm/sha512-ppc.pl
@@ -20,7 +20,7 @@
20# 20#
21# (*) 64-bit code in 32-bit application context, which actually is 21# (*) 64-bit code in 32-bit application context, which actually is
22# on TODO list. It should be noted that for safe deployment in 22# on TODO list. It should be noted that for safe deployment in
23# 32-bit *mutli-threaded* context asynchronous signals should be 23# 32-bit *multi-threaded* context asynchronous signals should be
24# blocked upon entry to SHA512 block routine. This is because 24# blocked upon entry to SHA512 block routine. This is because
25# 32-bit signaling procedure invalidates upper halves of GPRs. 25# 32-bit signaling procedure invalidates upper halves of GPRs.
26# Context switch procedure preserves them, but not signaling:-( 26# Context switch procedure preserves them, but not signaling:-(