diff options
Diffstat (limited to 'src/lib/libcrypto/modes/gcm128.c')
-rw-r--r-- | src/lib/libcrypto/modes/gcm128.c | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/lib/libcrypto/modes/gcm128.c b/src/lib/libcrypto/modes/gcm128.c index 2540b7cf3d..8136c2cde2 100644 --- a/src/lib/libcrypto/modes/gcm128.c +++ b/src/lib/libcrypto/modes/gcm128.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* $OpenBSD: gcm128.c,v 1.50 2025/06/08 07:49:45 jsing Exp $ */ | 1 | /* $OpenBSD: gcm128.c,v 1.51 2025/06/09 14:28:34 jsing Exp $ */ |
2 | /* ==================================================================== | 2 | /* ==================================================================== |
3 | * Copyright (c) 2010 The OpenSSL Project. All rights reserved. | 3 | * Copyright (c) 2010 The OpenSSL Project. All rights reserved. |
4 | * | 4 | * |
@@ -259,7 +259,6 @@ CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, void *key, block128_f block) | |||
259 | ctx->H.u[1] = be64toh(ctx->H.u[1]); | 259 | ctx->H.u[1] = be64toh(ctx->H.u[1]); |
260 | 260 | ||
261 | # if defined(GHASH_ASM_X86_OR_64) | 261 | # if defined(GHASH_ASM_X86_OR_64) |
262 | # if !defined(GHASH_ASM_X86) || defined(OPENSSL_IA32_SSE2) | ||
263 | /* check FXSR and PCLMULQDQ bits */ | 262 | /* check FXSR and PCLMULQDQ bits */ |
264 | if ((crypto_cpu_caps_ia32() & (CPUCAP_MASK_FXSR | CPUCAP_MASK_PCLMUL)) == | 263 | if ((crypto_cpu_caps_ia32() & (CPUCAP_MASK_FXSR | CPUCAP_MASK_PCLMUL)) == |
265 | (CPUCAP_MASK_FXSR | CPUCAP_MASK_PCLMUL)) { | 264 | (CPUCAP_MASK_FXSR | CPUCAP_MASK_PCLMUL)) { |
@@ -268,14 +267,9 @@ CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, void *key, block128_f block) | |||
268 | ctx->ghash = gcm_ghash_clmul; | 267 | ctx->ghash = gcm_ghash_clmul; |
269 | return; | 268 | return; |
270 | } | 269 | } |
271 | # endif | ||
272 | gcm_init_4bit(ctx->Htable, ctx->H.u); | 270 | gcm_init_4bit(ctx->Htable, ctx->H.u); |
273 | # if defined(GHASH_ASM_X86) /* x86 only */ | 271 | # if defined(GHASH_ASM_X86) /* x86 only */ |
274 | # if defined(OPENSSL_IA32_SSE2) | ||
275 | if (crypto_cpu_caps_ia32() & CPUCAP_MASK_SSE) { /* check SSE bit */ | ||
276 | # else | ||
277 | if (crypto_cpu_caps_ia32() & CPUCAP_MASK_MMX) { /* check MMX bit */ | 272 | if (crypto_cpu_caps_ia32() & CPUCAP_MASK_MMX) { /* check MMX bit */ |
278 | # endif | ||
279 | ctx->gmult = gcm_gmult_4bit_mmx; | 273 | ctx->gmult = gcm_gmult_4bit_mmx; |
280 | ctx->ghash = gcm_ghash_4bit_mmx; | 274 | ctx->ghash = gcm_ghash_4bit_mmx; |
281 | } else { | 275 | } else { |