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author | Mike Pall <mike> | 2010-08-31 00:05:10 +0200 |
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committer | Mike Pall <mike> | 2010-08-31 00:05:10 +0200 |
commit | 4ef6564f2e07c10336bcc59cc33d36ddef42176d (patch) | |
tree | 5ade7d5ba374df736c0cd64506aa115d4eada397 /src | |
parent | c7f91f8cd1c64031d6f74e957f6ad72f0bc8cf10 (diff) | |
download | luajit-4ef6564f2e07c10336bcc59cc33d36ddef42176d.tar.gz luajit-4ef6564f2e07c10336bcc59cc33d36ddef42176d.tar.bz2 luajit-4ef6564f2e07c10336bcc59cc33d36ddef42176d.zip |
PPC: Add instruction/call decode + dispatch macros.
Diffstat (limited to 'src')
-rw-r--r-- | src/buildvm_ppc.dasc | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/src/buildvm_ppc.dasc b/src/buildvm_ppc.dasc index c76c425d..8d3d3a70 100644 --- a/src/buildvm_ppc.dasc +++ b/src/buildvm_ppc.dasc | |||
@@ -139,6 +139,73 @@ | |||
139 | | | 139 | | |
140 | |//----------------------------------------------------------------------- | 140 | |//----------------------------------------------------------------------- |
141 | | | 141 | | |
142 | |// Access to frame relative to BASE. | ||
143 | |.define FRAME_PC, -8 | ||
144 | |.define FRAME_FUNC, -4 | ||
145 | | | ||
146 | |// Instruction decode. | ||
147 | |.macro decode_OP4, dst, ins; rlwinm dst, ins, 2, 22, 29; .endmacro | ||
148 | |.macro decode_RA8, dst, ins; rlwinm dst, ins, 27, 21, 28; .endmacro | ||
149 | |.macro decode_RB8, dst, ins; rlwinm dst, ins, 11, 21, 28; .endmacro | ||
150 | |.macro decode_RC8, dst, ins; rlwinm dst, ins, 19, 21, 28; .endmacro | ||
151 | |.macro decode_RD8, dst, ins; rlwinm dst, ins, 19, 13, 28; .endmacro | ||
152 | | | ||
153 | |.macro decode_OP1, dst, ins; rlwinm dst, ins, 0, 24, 31; .endmacro | ||
154 | |.macro decode_RD4, dst, ins; rlwinm dst, ins, 18, 14, 29; .endmacro | ||
155 | | | ||
156 | |// Instruction decode+dispatch. | ||
157 | |.macro ins_NEXT | ||
158 | | lwz INS, 0(PC) | ||
159 | | addi PC, PC, 4 | ||
160 | | decode_OP4 TMP0, INS | ||
161 | | decode_RB8 RB, INS | ||
162 | | lwzx TMP0, DISPATCH, TMP0 | ||
163 | | decode_RD8 RD, INS | ||
164 | | decode_RC8 RC, INS | ||
165 | | mtctr TMP0 | ||
166 | | decode_RA8 RA, INS | ||
167 | | bctr | ||
168 | |.endmacro | ||
169 | | | ||
170 | |// Instruction footer. | ||
171 | |.if 1 | ||
172 | | // Replicated dispatch. Less unpredictable branches, but higher I-Cache use. | ||
173 | | .define ins_next, ins_NEXT | ||
174 | | .define ins_next_, ins_NEXT | ||
175 | |.else | ||
176 | | // Common dispatch. Lower I-Cache use, only one (very) unpredictable branch. | ||
177 | | // Affects only certain kinds of benchmarks (and only with -j off). | ||
178 | | .macro ins_next | ||
179 | | b ->ins_next | ||
180 | | .endmacro | ||
181 | | .macro ins_next_ | ||
182 | | ->ins_next: | ||
183 | | ins_NEXT | ||
184 | | .endmacro | ||
185 | |.endif | ||
186 | | | ||
187 | |// Call decode and dispatch. | ||
188 | |.macro ins_callt | ||
189 | | // BASE = new base, RB = LFUNC/CFUNC, RC = nargs*8, FRAME_PC(BASE) = PC | ||
190 | | lwz PC, LFUNC:RB->pc | ||
191 | | lwz INS, 0(PC) | ||
192 | | addi PC, PC, 4 | ||
193 | | decode_OP4 TMP0, INS | ||
194 | | decode_RA8 RA, INS | ||
195 | | lwzx TMP0, DISPATCH, TMP0 | ||
196 | | add RA, RA, BASE | ||
197 | | mtctr TMP0 | ||
198 | | bctr | ||
199 | |.endmacro | ||
200 | | | ||
201 | |.macro ins_call | ||
202 | | // BASE = new base, RB = LFUNC/CFUNC, RC = nargs*8, PC = caller PC | ||
203 | | stw PC, FRAME_PC(BASE) | ||
204 | | ins_callt | ||
205 | |.endmacro | ||
206 | | | ||
207 | |//----------------------------------------------------------------------- | ||
208 | | | ||
142 | |// Assumes DISPATCH is relative to GL. | 209 | |// Assumes DISPATCH is relative to GL. |
143 | #define DISPATCH_GL(field) (GG_DISP2G + (int)offsetof(global_State, field)) | 210 | #define DISPATCH_GL(field) (GG_DISP2G + (int)offsetof(global_State, field)) |
144 | #define DISPATCH_J(field) (GG_DISP2J + (int)offsetof(jit_State, field)) | 211 | #define DISPATCH_J(field) (GG_DISP2J + (int)offsetof(jit_State, field)) |