Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | DynASM: Fix warning. | Mike Pall | 2017-03-08 | 1 | -1/+2 | |
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* | | MIPS64, part 2: Add MIPS64 hard-float JIT compiler backend. | Mike Pall | 2017-02-20 | 14 | -199/+1024 | |
| | | | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. Sponsored by Cisco Systems, Inc. | |||||
* | | Fix FOLD rules for math.abs() and FP negation. | Mike Pall | 2017-02-20 | 1 | -4/+11 | |
| | | | | | | | | Broken since SIMD constants were switched to IR_FLOAD REF_NIL. | |||||
* | | Fix soft-float math.abs() and negation. | Mike Pall | 2017-02-20 | 1 | -1/+2 | |
| | | | | | | | | Broken since SIMD constants were switched to IR_FLOAD REF_NIL. | |||||
* | | x64/LJ_GC64: Fix warning for DUALNUM build. | Mike Pall | 2017-02-20 | 1 | -1/+1 | |
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* | | x64/LJ_GC64: Fix (currently unused) integer stores in asm_tvptr(). | Mike Pall | 2017-02-20 | 1 | -1/+2 | |
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* | | ARM64: Cleanup and de-cargo-cult TValue store generation. | Mike Pall | 2017-02-20 | 1 | -49/+27 | |
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* | | Merge branch 'master' into v2.1 | Mike Pall | 2017-02-20 | 2 | -12/+10 | |
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| * | MIPS: Don't use RID_GP as a scratch register. | Mike Pall | 2017-02-20 | 1 | -3/+4 | |
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| * | MIPS: Fix emitted code for U32 to float conversion. | Mike Pall | 2017-02-20 | 1 | -11/+7 | |
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| * | MIPS: Backport workaround for compact unwind tables. | Mike Pall | 2017-02-20 | 2 | -0/+7 | |
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* | | Make checkptrGC() actually work. | Mike Pall | 2017-02-20 | 1 | -8/+3 | |
| | | | | | | | | | | Neither LJ_64 nor LJ_GC64 are defined when lj_def.h is included. So we'll need to use lazy C macro evaluation. | |||||
* | | ARM64: Fix AREF/HREF/UREF fusion. | Mike Pall | 2017-02-16 | 1 | -1/+1 | |
| | | | | | | | | Thanks to Zhongwei Yao. | |||||
* | | Fix extension docs about package.searchers. | Mike Pall | 2017-01-18 | 1 | -1/+1 | |
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* | | Merge branch 'master' into v2.1 | Mike Pall | 2017-01-17 | 197 | -216/+216 | |
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| * | Bump copyright date to 2017. | Mike Pall | 2017-01-17 | 177 | -195/+195 | |
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* | | LJ_GC64: Add build options and install instructions. | Mike Pall | 2017-01-17 | 4 | -7/+22 | |
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* | | Add some more extensions from Lua 5.2/5.3. | Mike Pall | 2017-01-17 | 7 | -11/+56 | |
| | | | | | | | | Contributed by François Perrad. | |||||
* | | Merge branch 'master' into v2.1 | Mike Pall | 2017-01-17 | 1 | -3/+3 | |
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| * | Fix HTML formatting. | Mike Pall | 2017-01-17 | 1 | -3/+3 | |
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* | | Merge branch 'master' into v2.1 | Mike Pall | 2017-01-17 | 1 | -1/+1 | |
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| * | Fix cross-endian jit.bcsave for MIPS target. | Mike Pall | 2017-01-17 | 1 | -1/+1 | |
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* | | ARM64: Remove unused variables in disassembler. | Mike Pall | 2016-12-30 | 1 | -4/+1 | |
| | | | | | | | | Thanks to François Perrad. | |||||
* | | ARM64: Fuse BOR/BXOR and BNOT into ORN/EON. | Mike Pall | 2016-12-15 | 2 | -17/+36 | |
| | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. | |||||
* | | Merge branch 'master' into v2.1 | Mike Pall | 2016-12-15 | 0 | -0/+0 | |
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| * | Add "proto" field to jit.util.funcinfo(). | Mike Pall | 2016-12-15 | 1 | -0/+1 | |
| | | | | | | | | Backport. | |||||
* | | Add "proto" field to jit.util.funcinfo(). | Mike Pall | 2016-12-13 | 1 | -0/+1 | |
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* | | ARM64: Use the correct FUSE check. | Mike Pall | 2016-12-09 | 1 | -8/+9 | |
| | | | | | | | | Oops, my bad. | |||||
* | | ARM64: Fuse BOR(BSHL, BSHR) into EXTR/ROR. | Mike Pall | 2016-12-09 | 1 | -1/+35 | |
| | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. | |||||
* | | Add missing FOLD rule for 64 bit shift+BAND simplification. | Mike Pall | 2016-12-08 | 1 | -0/+13 | |
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* | | ARM64: Fix code generation for S19 offsets. | Mike Pall | 2016-12-08 | 3 | -4/+4 | |
| | | | | | | | | Contributed by Zhongwei Yao. | |||||
* | | ARM64: Fuse various BAND/BSHL/BSHR/BSAR combinations. | Mike Pall | 2016-12-08 | 1 | -6/+54 | |
| | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. | |||||
* | | ARM64: Fuse FP multiply-add/sub. | Mike Pall | 2016-12-08 | 2 | -2/+30 | |
| | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. | |||||
* | | ARM64: Fuse XLOAD/XSTORE with STRREF/ADD/BSHL/CONV. | Mike Pall | 2016-12-07 | 1 | -6/+47 | |
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* | | ARM64: Reorganize operand extension definitions. | Mike Pall | 2016-12-07 | 2 | -6/+9 | |
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* | | ARM64: Add missing ldrb/strb instructions to disassembler. | Mike Pall | 2016-12-07 | 1 | -5/+9 | |
| | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. | |||||
* | | ARM64: Fix pc-relative loads of consts. Cleanup branch codegen. | Mike Pall | 2016-12-07 | 1 | -17/+13 | |
| | | | | | | | | Thanks to Zhongwei Yao. | |||||
* | | ARM64: Make use of tbz/tbnz and cbz/cbnz. | Mike Pall | 2016-11-29 | 3 | -17/+91 | |
| | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. | |||||
* | | Document 47 bit limit for lightuserdata. | Mike Pall | 2016-11-25 | 1 | -0/+11 | |
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* | | Eliminate use of lightuserdata derived from static data pointers. | Mike Pall | 2016-11-24 | 2 | -6/+5 | |
| | | | | | | | | Required for >47 bit VA, e.g. ARM64. | |||||
* | | ARM64: Emit more efficient trace exits. | Mike Pall | 2016-11-24 | 3 | -60/+56 | |
| | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. | |||||
* | | Merge branch 'master' into v2.1 | Mike Pall | 2016-11-21 | 1 | -0/+7 | |
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| * | Update contact info. | Mike Pall | 2016-11-21 | 1 | -0/+7 | |
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* | | Generalize deferred constant handling in backend to 64 bit. | Mike Pall | 2016-11-21 | 4 | -8/+34 | |
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* | | ARM64: Reject special case in emit_isk13(). | Mike Pall | 2016-11-20 | 1 | -1/+3 | |
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* | | ARM64: Allow full VA range for mcode allocation. | Mike Pall | 2016-11-20 | 1 | -0/+3 | |
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* | | ARM64: Add JIT compiler backend. | Mike Pall | 2016-11-20 | 12 | -24/+3887 | |
| | | | | | | | | | | Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com. Sponsored by Cisco Systems, Inc. | |||||
* | | Whitespace. | Mike Pall | 2016-11-20 | 1 | -1/+1 | |
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* | | Fix amalgamated build. | Mike Pall | 2016-11-19 | 1 | -1/+1 | |
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* | | Increase range of GG_State loads via IR_FLOAD with REF_NIL. | Mike Pall | 2016-11-19 | 4 | -6/+8 | |
| | | | | | | | | | | Require 32 bit alignment and store offset/4 instead. Otherwise this can overflow the 10 bit limit for the FOLD op2 key. |